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[23.128.96.18]) by mx.google.com with ESMTP id e10si8425599edj.183.2021.09.17.02.17.48; Fri, 17 Sep 2021 02:18:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kj9Y8gcT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236075AbhIPVnj (ORCPT + 99 others); Thu, 16 Sep 2021 17:43:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235627AbhIPVni (ORCPT ); Thu, 16 Sep 2021 17:43:38 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D041C061764 for ; Thu, 16 Sep 2021 14:42:17 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id b15so5616144lfe.7 for ; Thu, 16 Sep 2021 14:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ngsmooqXNsHgBKfkElGn8tQBGgJkqsh0GOhjTmfiKjs=; b=Kj9Y8gcTt4TgGUzYJFJ2xQFSkgUMMob94bgC1CKrrISQc/ZSgNlmv+sU681xqDsY9r Vwr2bEDqT4PrrP6NGXbI6Q6hxkGHLgXD+s5jnc8DEjWnPw9wsqsHMrCxxcYEKh8GzUJL +DPg40KBstQlzyJnALmo5nNGSDc73CSMDqayIMQKLpz79awy/N2BZe7+6NM2rVYXH7nK IX1v5ScwZvAdt0W6wT8BvHgVja6ZNrNpHFuEUy9w8PPKzRYMAYJuXznsbmI2uZUVfZkv iq79DmuCJVmruIvZjE4/I++5RjQckQuo6GeO+jAit+ESWIQe8n7O5SzLuipGCAi1UM9E ObSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ngsmooqXNsHgBKfkElGn8tQBGgJkqsh0GOhjTmfiKjs=; b=GgfVklfBl+oQUjhPjhfWRmr+vgPtiYdLdXA3qxBQ/nzT441P0/zxGEwb9+S0n9kUuu oeSTkPwnaZ7TiOlKtr50f5kK6Tr9QrsLnrumbS7fdXk1TKDygG2A3yfY1VUW738Y8bOD Glmkbh9G8euTfiLCYHTX0eWw3DkAcreSVGqhzoGVL6DcwRJUWjpZrA7IgVWCXh99DVV7 2KKmT3T6D509qMx/N+OZrNpp22d2/4JltmF27C/oC3w6cPPW9C+KsNCyRmZEnld0E3S7 trrEGuUrCT2p3+20WsElNxXvcSNph3eY/6rASFVY6E6XQJ3PtlvmTzwb5DuNx2u6Ibvi gYxQ== X-Gm-Message-State: AOAM532wrVM+/WeAMy7VgNSb2TrnxL8s2Qn/kturi9kpPyzhqKttj/hq T7uNuXyq2t44txzQMTB6doaWnqYcAEODN7j0eUof8Q== X-Received: by 2002:a05:6512:3c92:: with SMTP id h18mr5542169lfv.656.1631828535849; Thu, 16 Sep 2021 14:42:15 -0700 (PDT) MIME-Version: 1.0 References: <20210824164801.28896-1-lakshmi.sowjanya.d@intel.com> <20210824164801.28896-8-lakshmi.sowjanya.d@intel.com> In-Reply-To: <20210824164801.28896-8-lakshmi.sowjanya.d@intel.com> From: Linus Walleij Date: Thu, 16 Sep 2021 23:42:04 +0200 Message-ID: Subject: Re: [RFC PATCH v1 07/20] gpio: Add output event generation method to GPIOLIB and PMC Driver To: "D, Lakshmi Sowjanya" , "thierry.reding@gmail.com" , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Lee Jones , "open list:PWM SUBSYSTEM" Cc: "open list:GPIO SUBSYSTEM" , Bartosz Golaszewski , linux-kernel , Mark Gross , Andy Shevchenko , "Saha, Tamal" , bala.senthil@intel.com, Dipen Patel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lakshmi, On Tue, Aug 24, 2021 at 6:48 PM wrote: > From: Lakshmi Sowjanya D > > Intel Timed I/O hardware supports output scheduled in hardware. Enable > this functionality using GPIOlib > > Adds GPIOlib generate_output() hook into the driver. The driver is > supplied with a timestamp in terms of realtime system clock (the same > used for input timestamping). The driver must know how to translate this > into a timebase meaningful for the hardware. > > Adds userspace write() interface. Output can be selected using the line > event create ioctl. The write() interface takes a single timestamp > event request parameter. An output edge rising or falling is generated > for each event request. > > The user application supplies a trigger time in terms of the realtime > clock the driver converts this into the corresponding ART clock value > that is used to 'arm' the output. > > Work around device quirk that doesn't allow the output to be explicitly > set. Instead, count the output edges and insert an additional edge as > needed to reset the output to zero. > > Co-developed-by: Christopher Hall > Signed-off-by: Christopher Hall > Signed-off-by: Tamal Saha > Signed-off-by: Lakshmi Sowjanya D > Reviewed-by: Mark Gross So this is some street organ machine that generates sequences with determined timing between positive and negative edges right? I can't see how this hardware is different from a PWM, or well I do to some extent, you can control the period of several subsequent waves, but that is really just an elaborate version of PWM in my book. It seems to me that this part of the functionality belongs in the PWM subsystem which already has interfaces for similar things, and you should probably extend PWM to handle random waveforms rather than trying to shoehorn this into the GPIO subsystem. Yours, Linus Walleij