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[23.128.96.18]) by mx.google.com with ESMTP id qk36si7419657ejc.207.2021.09.17.06.34.39; Fri, 17 Sep 2021 06:35:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343782AbhIQJ2b (ORCPT + 99 others); Fri, 17 Sep 2021 05:28:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:45976 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245690AbhIQJVq (ORCPT ); Fri, 17 Sep 2021 05:21:46 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2AF8A611CA; Fri, 17 Sep 2021 09:20:24 +0000 (UTC) Received: from [198.52.44.129] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mRA2g-00BKuT-9Q; Fri, 17 Sep 2021 10:20:22 +0100 Date: Fri, 17 Sep 2021 10:20:21 +0100 Message-ID: <87lf3vblt6.wl-maz@kernel.org> From: Marc Zyngier To: "Sven Peter" Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, "Bjorn Helgaas" , "Rob Herring" , "Lorenzo Pieralisi" , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , "Alyssa Rosenzweig" , "Stan Skowronek" , "Mark Kettenis" , "Hector Martin" , "Robin Murphy" , kernel-team@android.com Subject: Re: [PATCH v3 04/10] PCI: apple: Add initial hardware bring-up In-Reply-To: <6eb53661-e11e-4634-9fa5-5e7e62d57a15@www.fastmail.com> References: <20210913182550.264165-1-maz@kernel.org> <20210913182550.264165-5-maz@kernel.org> <6eb53661-e11e-4634-9fa5-5e7e62d57a15@www.fastmail.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 198.52.44.129 X-SA-Exim-Rcpt-To: sven@svenpeter.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, kw@linux.com, alyssa@rosenzweig.io, stan@corellium.com, kettenis@openbsd.org, marcan@marcan.st, Robin.Murphy@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 13 Sep 2021 21:48:47 +0100, "Sven Peter" wrote: > > > > On Mon, Sep 13, 2021, at 20:25, Marc Zyngier wrote: > > From: Alyssa Rosenzweig > > > > Add a minimal driver to bring up the PCIe bus on Apple system-on-chips, > > particularly the Apple M1. This driver exposes the internal bus used for > > the USB type-A ports, Ethernet, Wi-Fi, and Bluetooth. Bringing up the > > radios requires additional drivers beyond what's necessary for PCIe > > itself. > > > > At this stage, nothing is functionnal. > > > > Co-developed-by: Stan Skowronek > > Signed-off-by: Stan Skowronek > > Signed-off-by: Alyssa Rosenzweig > > Signed-off-by: Marc Zyngier > > Link: https://lore.kernel.org/r/20210816031621.240268-3-alyssa@rosenzweig.io > > --- > > MAINTAINERS | 7 + > > drivers/pci/controller/Kconfig | 12 ++ > > drivers/pci/controller/Makefile | 1 + > > drivers/pci/controller/pcie-apple.c | 243 ++++++++++++++++++++++++++++ > > 4 files changed, 263 insertions(+) > > create mode 100644 drivers/pci/controller/pcie-apple.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 813a847e2d64..9905cc48fed9 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1280,6 +1280,13 @@ S: Maintained > > F: Documentation/devicetree/bindings/iommu/apple,dart.yaml > > F: drivers/iommu/apple-dart.c > > > > +APPLE PCIE CONTROLLER DRIVER > > +M: Alyssa Rosenzweig > > +M: Marc Zyngier > > +L: linux-pci@vger.kernel.org > > +S: Maintained > > +F: drivers/pci/controller/pcie-apple.c > > + > > APPLE SMC DRIVER > > M: Henrik Rydberg > > L: linux-hwmon@vger.kernel.org > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > > index 326f7d13024f..814833a8120d 100644 > > --- a/drivers/pci/controller/Kconfig > > +++ b/drivers/pci/controller/Kconfig > > @@ -312,6 +312,18 @@ config PCIE_HISI_ERR > > Say Y here if you want error handling support > > for the PCIe controller's errors on HiSilicon HIP SoCs > > > > +config PCIE_APPLE > > + tristate "Apple PCIe controller" > > + depends on ARCH_APPLE || COMPILE_TEST > > + depends on OF > > + depends on PCI_MSI_IRQ_DOMAIN > > + help > > + Say Y here if you want to enable PCIe controller support on Apple > > + system-on-chips, like the Apple M1. This is required for the USB > > + type-A ports, Ethernet, Wi-Fi, and Bluetooth. > > + > > + If unsure, say Y if you have an Apple Silicon system. > > + > > source "drivers/pci/controller/dwc/Kconfig" > > source "drivers/pci/controller/mobiveil/Kconfig" > > source "drivers/pci/controller/cadence/Kconfig" > > diff --git a/drivers/pci/controller/Makefile > > b/drivers/pci/controller/Makefile > > index aaf30b3dcc14..f9d40bad932c 100644 > > --- a/drivers/pci/controller/Makefile > > +++ b/drivers/pci/controller/Makefile > > @@ -37,6 +37,7 @@ obj-$(CONFIG_VMD) += vmd.o > > obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o > > obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o > > obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o > > +obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o > > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW > > obj-y += dwc/ > > obj-y += mobiveil/ > > diff --git a/drivers/pci/controller/pcie-apple.c > > b/drivers/pci/controller/pcie-apple.c > > new file mode 100644 > > index 000000000000..f3c414950a10 > > --- /dev/null > > +++ b/drivers/pci/controller/pcie-apple.c > > @@ -0,0 +1,243 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * PCIe host bridge driver for Apple system-on-chips. > > + * > > + * The HW is ECAM compliant, so once the controller is initialized, > > + * the driver mostly deals MSI mapping and handling of per-port > > + * interrupts (INTx, management and error signals). > > + * > > + * Initialization requires enabling power and clocks, along with a > > + * number of register pokes. > > + * > > + * Copyright (C) 2021 Alyssa Rosenzweig > > + * Copyright (C) 2021 Google LLC > > + * Copyright (C) 2021 Corellium LLC > > + * Copyright (C) 2021 Mark Kettenis > > + * > > + * Author: Alyssa Rosenzweig > > + * Author: Marc Zyngier > > + */ > > + > > [...] > > + > > +static inline void rmwl(u32 clr, u32 set, void __iomem *addr) > > +{ > > + writel_relaxed((readl_relaxed(addr) & ~clr) | set, addr); > > +} > > This helper is a bit strange, especially since it's always only used > with either clr != 0 or set != 0 but never (clr = 0 and set = 0) afaict. > Maybe create two instead for setting and clearing bits? That's indeed nicer, and it makes the code more readable. > > > + > > +static int apple_pcie_setup_port(struct apple_pcie *pcie, > > + struct device_node *np) > > +{ > > + struct platform_device *platform = to_platform_device(pcie->dev); > > + struct apple_pcie_port *port; > > + struct gpio_desc *reset; > > + u32 stat, idx; > > + int ret; > > + > > + reset = gpiod_get_from_of_node(np, "reset-gpios", 0, > > + GPIOD_OUT_LOW, "#PERST"); > > + if (IS_ERR(reset)) > > + return PTR_ERR(reset); > > + > > + port = devm_kzalloc(pcie->dev, sizeof(*port), GFP_KERNEL); > > + if (!port) > > + return -ENOMEM; > > + > > + ret = of_property_read_u32_index(np, "reg", 0, &idx); > > + if (ret) > > + return ret; > > + > > + /* Use the first reg entry to work out the port index */ > > + port->idx = idx >> 11; > > + port->pcie = pcie; > > + port->np = np; > > + > > + port->base = devm_platform_ioremap_resource(platform, port->idx + 2); > > + if (IS_ERR(port->base)) > > + return -ENODEV; > > + > > + rmwl(0, PORT_APPCLK_EN, port + PORT_APPCLK); > > + > > + rmwl(0, PORT_PERST_OFF, port->base + PORT_PERST); > > + gpiod_set_value(reset, 1); > > + > > + ret = readl_relaxed_poll_timeout(port->base + PORT_STATUS, stat, > > + stat & PORT_STATUS_READY, 100, 250000); > > + if (ret < 0) { > > + dev_err(pcie->dev, "port %pOF ready wait timeout\n", np); > > + return ret; > > + } > > + > > + /* Flush writes and enable the link */ > > + dma_wmb(); > > This is a DMA barrier but there's no DMA you need to order this against > here. I think you can just drop it. Indeed, this is all MMIO based, and doesn't refer to anything in memory. Barrier gone. Thanks, M. -- Without deviation from the norm, progress is not possible.