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[23.128.96.18]) by mx.google.com with ESMTP id h15si5400674jaa.28.2021.09.17.07.44.26; Fri, 17 Sep 2021 07:44:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244515AbhIQMkZ (ORCPT + 99 others); Fri, 17 Sep 2021 08:40:25 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52306 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S240600AbhIQMkU (ORCPT ); Fri, 17 Sep 2021 08:40:20 -0400 X-UUID: ed5b0f4050da4da58f9a9a684d51620c-20210917 X-UUID: ed5b0f4050da4da58f9a9a684d51620c-20210917 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 581002337; Fri, 17 Sep 2021 20:38:54 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Sep 2021 20:38:53 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 17 Sep 2021 20:38:53 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Sep 2021 20:38:52 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring , Matthias Brugger CC: Chaotian Jing , Avri Altman , Wenbin Mei , Wolfram Sang , Yoshihiro Shimoda , Linus Walleij , Yue Hu , Bean Huo , Adrian Hunter , , , , , , "Rob Herring" Subject: [PATCH v4 1/3] dt-bindings: mmc: mtk-sd: add hs400 dly3 setting Date: Fri, 17 Sep 2021 20:38:49 +0800 Message-ID: <20210917123851.22741-2-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210917123851.22741-1-wenbin.mei@mediatek.com> References: <20210917123851.22741-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add hs400 dly3 setting for mtk-sd yaml Signed-off-by: Wenbin Mei Acked-by: Rob Herring Reviewed-by: Linus Walleij --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index e866e985549e..82768a807294 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -119,6 +119,18 @@ properties: If present, HS400 command responses are sampled on rising edges. If not present, HS400 command responses are sampled on falling edges. + mediatek,hs400-ds-dly3: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Gear of the third delay line for DS for input data latch in data + pad macro, there are 32 stages from 0 to 31. + For different corner IC, the time is different about one step, it is + about 100ps. + The value is confirmed by doing scan and calibration to find a best + value with corner IC and it is valid only for HS400 mode. + minimum: 0 + maximum: 31 + mediatek,latch-ck: $ref: /schemas/types.yaml#/definitions/uint32 description: -- 2.25.1