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Date:   Sat, 18 Sep 2021 22:17:13 +0800
From:   Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To:     Kefeng Wang <wangkefeng.wang@huawei.com>
Cc:     Chen Huang <chenhuang5@huawei.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Darius Rad <darius@bluespec.com>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses
Message-ID: <20210918221713.289f63bb@xhacker>
In-Reply-To: <9200c4c2-44b9-480e-6970-5188640fb00a@huawei.com>
References: <20210916130855.4054926-1-chenhuang5@huawei.com>
        <20210917221429.4d3a15ca@xhacker>
        <9200c4c2-44b9-480e-6970-5188640fb00a@huawei.com>
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On Sat, 18 Sep 2021 09:14:05 +0800
Kefeng Wang <wangkefeng.wang@huawei.com> wrote:

> On 2021/9/17 22:14, Jisheng Zhang wrote:
> > On Thu, 16 Sep 2021 13:08:53 +0000
> > Chen Huang <chenhuang5@huawei.com> wrote:
> > =20
> >> The patchset improves RISCV unaligned memory accesses, selects
> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> >> of unaligned memory accesses.
> >>
> >> If CPU don't support unaligned memory accesses for now, please
> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> >> don't support unaligned memory accesses, I don't choose the
> >> CONFIG for them. =20
> > This will break unified kernel Image for riscv. Obviously, we will have
> > two images for efficient unaligned access platforms and non-efficient
> > unaligned access platforms. IMHO, we may need alternative mechanism or
> > something else to dynamically enable related code path. =20
>=20
> it won't break unified kernel Image for riscv, if one SoC choose
>=20
> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

the "unified" means the kernel Image has to support all RV64GC or RV32GC So=
Cs.
To make the Image works for both efficient unaligned access and inefficient
unaligned access, I think we'd better make "inefficient unaligned access"
default behavior, the use alternative etc. tech to patch related code path
for efficient unaligned access.


>=20
> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

linux Distributions doesn't have enough background of which config options
must be enabled.

>=20
> similar configuration.

I have little knowledge of powerpc or m68k, but there are serveral different
defconfig files for arm, for example multi_v7_defconfig and multi_v5_defcon=
fig.
The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while
the later v5 doesn't. Will you persuade riscv maintainers to accept one more
defconfig file?

Thanks

>=20
> Yes,=C2=A0 it could be an optimization via alternative mechanism or somet=
hing=20
> else to
>=20
> dynamically enable related code path later.
>=20
> >
> > Regards
> > =20
> >> Changes since v1:
> >>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
> >>     unaligned memory accesses, add an option for CPUs to choose it or =
not.
> >>
> >> Chen Huang (2):
> >>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
> >>    riscv: Support DCACHE_WORD_ACCESS
> >>
> >>   arch/riscv/Kconfig                      |  5 ++++
> >>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++=
++
> >>   2 files changed, 42 insertions(+)
> >> =20
> >
> > .
> > =20