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From:   Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
To:     Mark Brown <broonie@kernel.org>
Cc:     Liam Girdwood <lgirdwood@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Heiko Stuebner <heiko@sntech.de>,
        linux-rockchip@lists.infradead.org, alsa-devel@alsa-project.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/4] dt-bindings: sound: add rockchip i2s-tdm binding
Date:   Sun, 19 Sep 2021 19:38:47 +0200
Message-ID: <2435067.tOv7cHfTnj@archbook>
In-Reply-To: <20210916122549.GF5048@sirena.org.uk>
References: <20210903231536.225540-1-frattaroli.nicolas@gmail.com> <42974939.Tn3hggVSkZ@archbook> <20210916122549.GF5048@sirena.org.uk>
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On Donnerstag, 16. September 2021 14:25:49 CEST Mark Brown wrote:
> On Wed, Sep 15, 2021 at 07:06:14PM +0200, Nicolas Frattaroli wrote:
> > On Mittwoch, 15. September 2021 16:10:12 CEST Mark Brown wrote:
> > > Why is this not part of the normal bus format configuration?  I don't
> > > know what this is but it sounds a lot like I2S mode...
> > 
> > This affects all TDM I2S modes, i.e. TDM Normal, TDM Left Justified and
> > TDM
> > Right Justified.
> > 
> > Without tdm-fsync-half-frame, we purportedly get the following output in
> > TDM Normal Mode (I2S Format):
> > (ch0l = channel 0 left, ch0r = channel 0 right)
> > 
> > fsync: 	_____________________________
> > 
> >                      	            \____________________________
> > 
> > sdi/sdo: ch0l, ch0r, ..., ch3l, ch3r,  ch0l, ch0r, ...
> > 
> > With tdm-fsync-half-frame, we purportedly get the following:
> > 
> > fsync: 	_____________________________
> > 
> >                      	            \____________________________
> > 
> > sdi/sdo: ch0l,  ch1l,  ch2l,  ch3l,   ch0r,  ch1r,  ch2r,  ch3r
> > 
> > At least, according to the TRM. I do not have an oscilloscope to verify
> > this myself, and in the following paragraphs, I will elaborate why this
> > seems confusing to me.
> 
> fsync-half-frame is just normal TDM for I2S, the default mode is how DSP
> mode normally operates.  I don't know that there's any pressing need to
> support mix'n'match here, you could but it should be through the TDM
> configuration API.
> 
> > So to answer the question, it's not part of the bus format because it
> > applies to three bus formats, and I'm completely out of my depth here and
> > wouldn't define three separate bus formats based on my own speculation of
> > how this works.
> 
> It is part of the bus format really.  I suspect the hardware is the kind
> that only really implements DSP mode and can just fake up a LRCLK for
> I2S in order to interoperate.

Thank you for your explanation!

Going forward, what would be a solution that is acceptable for upstream? As 
far as I understand, the obvious route here is to drop the rockchip,fsync-
half-frame property and just always set this mode when we're using a TDM bus 
format. Is this correct?

According to the TRM, the register bit this sets only affects TDM modes. 
Though since TDM is not standardised in any way from what I've read online, it 
is possible that there is hardware out there which expects the non-fsync-half-
frame mode, but I am completely fine with only thinking about this hardware 
when it actually surfaces.

Regards,
Nicolas Frattaroli