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[23.128.96.18]) by mx.google.com with ESMTP id z21si17237694eji.707.2021.09.20.06.42.15; Mon, 20 Sep 2021 06:42:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236354AbhITJQK (ORCPT + 99 others); Mon, 20 Sep 2021 05:16:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:54012 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229689AbhITJPd (ORCPT ); Mon, 20 Sep 2021 05:15:33 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 098F860ED7; Mon, 20 Sep 2021 09:14:07 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mSFNE-00Bj7S-QY; Mon, 20 Sep 2021 10:14:05 +0100 Date: Mon, 20 Sep 2021 10:14:04 +0100 Message-ID: <871r5jwqw3.wl-maz@kernel.org> From: Marc Zyngier To: Kishon Vijay Abraham I Cc: Thomas Gleixner , Bjorn Helgaas , , , Lorenzo Pieralisi , Subject: Re: [PATCH 0/3] PCI/gic-v3-its: Add support for same ITS device ID for multiple PCIe devices In-Reply-To: <20210920064133.14115-1-kishon@ti.com> References: <20210920064133.14115-1-kishon@ti.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kishon@ti.com, tglx@linutronix.de, bhelgaas@google.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lorenzo.pieralisi@arm.com, lokeshvutla@ti.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 20 Sep 2021 07:41:30 +0100, Kishon Vijay Abraham I wrote: > > AM64 has an issue in that it doesn't trigger interrupt if the address > in the *pre_its_window* is not aligned to 8-bytes (this is due to an > invalid bridge configuration in HW). > > This means there will not be interrupts for devices with PCIe > requestor ID 0x1, 0x3, 0x5..., as the address in the pre-ITS window > would be 4 (1 << 2), 12 (3 << 2), 20 (5 << 2) respectively which are > not aligned to 8-bytes. > > The DT binding has specified "msi-map-mask" using which multiple PCIe > devices could be made to use the same ITS device ID. > > Add support in irq-gic-v3-its-pci-msi.c for such cases where multiple > PCIe devices are using the same ITS device ID. > > Kishon Vijay Abraham I (3): > PCI: Add support in pci_walk_bus() to invoke callback matching RID > PCI: Export find_pci_root_bus() > irqchip/gic-v3-its: Include "msi-map-mask" for calculating nvecs > > drivers/irqchip/irq-gic-v3-its-pci-msi.c | 21 ++++++++++++++++++++- > drivers/pci/bus.c | 13 +++++++++---- > drivers/pci/host-bridge.c | 3 ++- > include/linux/pci.h | 8 ++++++-- > 4 files changed, 37 insertions(+), 8 deletions(-) What I don't see in this series is how you address the other part of the problem, which is your reuse of the Socionext hack. Please post a complete series addressing all the issues for this HW. Thanks, M. -- Without deviation from the norm, progress is not possible.