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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id 25sm22965108wmo.9.2021.09.20.06.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 06:04:16 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2 5/5] riscv: dts: sifive: add missing compatible for plic Date: Mon, 20 Sep 2021 15:04:12 +0200 Message-Id: <20210920130412.145231-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210920130248.145058-1-krzysztof.kozlowski@canonical.com> References: <20210920130248.145058-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add proper compatible for Platform-Level Interrupt Controller to silence dtbs_check warnings: interrupt-controller@c000000: compatible: ['sifive,plic-1.0.0'] is too short Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. None --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 7db861053483..0655b5c4201d 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -141,7 +141,7 @@ soc { ranges; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <53>; interrupt-controller; -- 2.30.2