Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp2191844pxb; Mon, 20 Sep 2021 14:51:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyogH+vomE1v7a977sm3mQnkRb6a2C5gFmKhf7d72NydPQQAL6kSLJaJcwiq3IozAQ6D++W X-Received: by 2002:a6b:fe05:: with SMTP id x5mr14536289ioh.26.1632174714781; Mon, 20 Sep 2021 14:51:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632174714; cv=none; d=google.com; s=arc-20160816; b=Osv3i5lvKFXogn5pHzL2oY1iEbBO2dwkFAIlrEIN2nan7OJMS48e2xggqHIPgIi/Ym DUVN5SssVC2fQgr43RfBRLD/0aueDDYYQKgVwOEqv86XsOUjx9c9I4OCsyfyYm3wKf3I GElWu5gB4rA9dkCYwv192U9G8hOTIPMhdfZvsscnJy/KigNOqrS6W39txAnbdhh8tj2k FQx2T43tjNFC/9LKtDRoBja/bPkPIKDlZFIKGK+aoBSFZL/rWOUmz9eU7to6y0NRbSNn w4tMn4DZBCVjePo4xjwcJS6P94LNZq/92oHKr7/iZ4yJA4bmlT0buD4rAAaQ6Ei2k5Tl t0DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=qvuKv4X0PMd2/qJL/b3/tj4zulPLbZJqPf1rlW9sG6U=; b=QAkUXXMo3d3C4xjs3gNv+aRVCCaxi2P1u7PreAq/9J8XOVjdpfBOCu0mqntLTw381s xhb7CUMEuW8C6VuD/lECnBngtFHKsZC1Xrhhl5s7iz1Y/WcXkKrLL7ZyXDqxEiLXpNAv jQCXOylyi5SOX5db1YmjKM4B8Kb24iyt/2Mp2zLL2hzerR2W7qPm5eCVId4HULO22z/g hlk1txYJHbliJQeb1UDXVrq2x9tiVlEHh8ZFJwNt0ITZ+Sd9u90LVk6FHgB0YWSAtPxJ 4bEVGAJfDIChcg0CoSrxcHMesTzlfRpCK/chlYGjsT6KISQ85osBIp+jT7B9SoLEA3SK Ed6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=DeJ1xOEs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id d8si15101734ila.45.2021.09.20.14.51.43; Mon, 20 Sep 2021 14:51:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=DeJ1xOEs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235501AbhITMoL (ORCPT + 99 others); Mon, 20 Sep 2021 08:44:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:34836 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234162AbhITMoK (ORCPT ); Mon, 20 Sep 2021 08:44:10 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id D905660F43; Mon, 20 Sep 2021 12:42:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632141763; bh=LJd326Onj4XtLEwt35NMphBK1paSjnbTcGe5Aoy65Mg=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=DeJ1xOEstl5+CzNf5BKwpkGnrbneFDGVk5At3W8ysipTWc8z+u9S1YNrQkNsV0TMQ oZ2q5CrK92h44aq6/Lm8db0Pyk9wuAVYuYAyl4gqBhUhT7xS+bkHpq8COsHw33o8QK aYO3l9R/XW5AnHhK+zuDV4Q2vX9D2C70wTOeDgE8aBWqXcgiWn5bl+GDG851KP00Gb ndatDskBGCB87CDK8SsejrzEgTsvRw9MJxVpOHynCqsSWAIj++R/8ff6P1fcfPXMwn GCrw8K7/eFZOxlJxz8aSwLaYfYesetfUVro0ijMII/5EQ/Lb3fuNHpe0+bcI012RSv kBjlThj7ZBJyQ== Received: by mail-ed1-f41.google.com with SMTP id bx4so16080361edb.4; Mon, 20 Sep 2021 05:42:43 -0700 (PDT) X-Gm-Message-State: AOAM532XEH6RvcE1qnczsi2PchEXyvXf8DkRbTvqX80OxfMKxJY2rYrB roTmHAPhdq5gmtxGWX8Yr11sWsxegHBjvHlifg== X-Received: by 2002:a17:906:7217:: with SMTP id m23mr27972643ejk.466.1632141762450; Mon, 20 Sep 2021 05:42:42 -0700 (PDT) MIME-Version: 1.0 References: <20210916084714.311048-1-zhang.lyra@gmail.com> <20210916084714.311048-3-zhang.lyra@gmail.com> In-Reply-To: From: Rob Herring Date: Mon, 20 Sep 2021 07:42:30 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/4] dt-bindings: clk: sprd: Add bindings for ums512 clock controller To: Chunyan Zhang Cc: Stephen Boyd , linux-clk , DTML , Baolin Wang , Orson Zhai , Chunyan Zhang , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 17, 2021 at 3:41 AM Chunyan Zhang wrote: > > On Thu, 16 Sept 2021 at 22:29, Rob Herring wrote: > > > > On Thu, Sep 16, 2021 at 04:47:12PM +0800, Chunyan Zhang wrote: > > > From: Chunyan Zhang > > > > > > Add a new bindings to describe ums512 clock compatible strings. > > > > > > Signed-off-by: Chunyan Zhang > > > --- > > > .../bindings/clock/sprd,ums512-clk.yaml | 106 ++++++++++++++++++ > > > 1 file changed, 106 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml > > > new file mode 100644 > > > index 000000000000..be3c37180279 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml > > > @@ -0,0 +1,106 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +# Copyright 2019-2021 Unisoc Inc. > > > +%YAML 1.2 > > > +--- > > > +$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#" > > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > > + > > > +title: UMS512 Clock Control Unit Device Tree Bindings > > > + > > > +maintainers: > > > + - Orson Zhai > > > + - Baolin Wang > > > + - Chunyan Zhang > > > + > > > +properties: > > > + "#clock-cells": > > > + const: 1 > > > + > > > + compatible: > > > + enum: > > > + - sprd,ums512-apahb-gate > > > + - sprd,ums512-ap-clk > > > + - sprd,ums512-aonapb-clk > > > + - sprd,ums512-pmu-gate > > > + - sprd,ums512-g0-pll > > > + - sprd,ums512-g2-pll > > > + - sprd,ums512-g3-pll > > > + - sprd,ums512-gc-pll > > > + - sprd,ums512-aon-gate > > > + - sprd,ums512-audcpapb-gate > > > + - sprd,ums512-audcpahb-gate > > > + - sprd,ums512-gpu-clk > > > + - sprd,ums512-mm-clk > > > + - sprd,ums512-mm-gate-clk > > > + - sprd,ums512-apapb-gate > > > + > > > + clocks: > > > + minItems: 1 > > > + maxItems: 4 > > > + description: | > > > + The input parent clock(s) phandle for this clock, only list fixed > > > + clocks which are declared in devicetree. > > > + > > > + clock-names: > > > + minItems: 1 > > > + maxItems: 4 > > > + items: > > > + - const: ext-26m > > > + - const: ext-32k > > > + - const: ext-4m > > > + - const: rco-100m > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > +required: > > > + - compatible > > > + - '#clock-cells' > > > + > > > +if: > > > + properties: > > > + compatible: > > > + enum: > > > + - sprd,ums512-ap-clk > > > + - sprd,ums512-aonapb-clk > > > + - sprd,ums512-mm-clk > > > +then: > > > + required: > > > + - reg > > > + > > > +else: > > > + description: | > > > + Other UMS512 clock nodes should be the child of a syscon node in > > > + which compatible string should be: > > > + "sprd,ums512-glbregs", "syscon", "simple-mfd" > > > + > > > + The 'reg' property for the clock node is also required if there is a sub > > > + range of registers for the clocks. > > > > In which cases is this not true? > > Seems not needed, I will remove 'reg' property for this kind of cases. Wrong direction. Please keep 'reg'. My question is why can't you always have it? That is the preference. Rob