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Wed, 22 Sep 2021 02:18:04 +0000 Subject: Re: [PATCH v3 4/9] drm/scheduler: Add fence deadline support To: Rob Clark Cc: dri-devel , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Daniel Vetter , =?UTF-8?Q?Christian_K=c3=b6nig?= , =?UTF-8?Q?Michel_D=c3=a4nzer?= , Pekka Paalanen , Rob Clark , David Airlie , Sumit Semwal , =?UTF-8?Q?Christian_K=c3=b6nig?= , Tian Tao , Steven Price , Melissa Wen , Luben Tuikov , Boris Brezillon , Jack Zhang , open list , "open list:DMA BUFFER SHARING FRAMEWORK" References: <20210903184806.1680887-1-robdclark@gmail.com> <20210903184806.1680887-5-robdclark@gmail.com> <101628ea-23c9-4bc0-5abc-a5b71b0fccc1@amd.com> From: Andrey Grodzovsky Message-ID: Date: Tue, 21 Sep 2021 22:18:01 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-ClientProxiedBy: YTOPR0101CA0001.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b00:15::14) To DM5PR12MB1947.namprd12.prod.outlook.com (2603:10b6:3:111::23) MIME-Version: 1.0 Received: from [IPv6:2607:fea8:3edf:49b0:591f:ecc8:119a:23e7] (2607:fea8:3edf:49b0:591f:ecc8:119a:23e7) by YTOPR0101CA0001.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b00:15::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.13 via Frontend Transport; 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>>> } >>> >>> +static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, >>> + ktime_t deadline) >>> +{ >>> + struct drm_sched_fence *fence = to_drm_sched_fence(f); >>> + unsigned long flags; >>> + >>> + spin_lock_irqsave(&fence->lock, flags); >>> + >>> + /* If we already have an earlier deadline, keep it: */ >>> + if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags) && >>> + ktime_before(fence->deadline, deadline)) { >>> + spin_unlock_irqrestore(&fence->lock, flags); >>> + return; >>> + } >>> + >>> + fence->deadline = deadline; >>> + set_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, &f->flags); >>> + >>> + spin_unlock_irqrestore(&fence->lock, flags); >>> + >>> + if (fence->parent) >>> + dma_fence_set_deadline(fence->parent, deadline); >>> +} >>> + >>> static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { >>> .get_driver_name = drm_sched_fence_get_driver_name, >>> .get_timeline_name = drm_sched_fence_get_timeline_name, >>> @@ -138,6 +162,7 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { >>> .get_driver_name = drm_sched_fence_get_driver_name, >>> .get_timeline_name = drm_sched_fence_get_timeline_name, >>> .release = drm_sched_fence_release_finished, >>> + .set_deadline = drm_sched_fence_set_deadline_finished, >>> }; >>> >>> struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f) >>> @@ -152,6 +177,15 @@ struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f) >>> } >>> EXPORT_SYMBOL(to_drm_sched_fence); >>> >>> +void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, >>> + struct dma_fence *fence) >>> +{ >>> + s_fence->parent = dma_fence_get(fence); >>> + if (test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT, >>> + &s_fence->finished.flags)) >>> + dma_fence_set_deadline(fence, s_fence->deadline); >> >> I believe above you should pass be s_fence->finished to >> dma_fence_set_deadline >> instead it fence which is the HW fence itself. > Hmm, unless this has changed recently with some patches I don't have, > s_fence->parent is the one signalled by hw, so it is the one we want > to set the deadline on > > BR, > -R No it didn't change. But then when exactly will drm_sched_fence_set_deadline_finished execute such that fence->parent != NULL ? In other words, I am not clear how propagation happens otherwise - if dma_fence_set_deadline is called with the HW fence then the assumption here is that driver provided driver specific dma_fence_ops.dma_fence_set_deadline callback executes but I was under impression that drm_sched_fence_set_deadline_finished is the one that propagates the deadline to the HW fence's callback and for it to execute dma_fence_set_deadline needs to be called with s_fence->finished. Andrey > >> Andrey >> >> >>> +} >>> + >>> struct drm_sched_fence *drm_sched_fence_alloc(struct drm_sched_entity *entity, >>> void *owner) >>> { >>> diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c >>> index 595e47ff7d06..27bf0ac0625f 100644 >>> --- a/drivers/gpu/drm/scheduler/sched_main.c >>> +++ b/drivers/gpu/drm/scheduler/sched_main.c >>> @@ -978,7 +978,7 @@ static int drm_sched_main(void *param) >>> drm_sched_fence_scheduled(s_fence); >>> >>> if (!IS_ERR_OR_NULL(fence)) { >>> - s_fence->parent = dma_fence_get(fence); >>> + drm_sched_fence_set_parent(s_fence, fence); >>> r = dma_fence_add_callback(fence, &sched_job->cb, >>> drm_sched_job_done_cb); >>> if (r == -ENOENT) >>> diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h >>> index 7f77a455722c..158ddd662469 100644 >>> --- a/include/drm/gpu_scheduler.h >>> +++ b/include/drm/gpu_scheduler.h >>> @@ -238,6 +238,12 @@ struct drm_sched_fence { >>> */ >>> struct dma_fence finished; >>> >>> + /** >>> + * @deadline: deadline set on &drm_sched_fence.finished which >>> + * potentially needs to be propagated to &drm_sched_fence.parent >>> + */ >>> + ktime_t deadline; >>> + >>> /** >>> * @parent: the fence returned by &drm_sched_backend_ops.run_job >>> * when scheduling the job on hardware. We signal the >>> @@ -505,6 +511,8 @@ void drm_sched_entity_set_priority(struct drm_sched_entity *entity, >>> enum drm_sched_priority priority); >>> bool drm_sched_entity_is_ready(struct drm_sched_entity *entity); >>> >>> +void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, >>> + struct dma_fence *fence); >>> struct drm_sched_fence *drm_sched_fence_alloc( >>> struct drm_sched_entity *s_entity, void *owner); >>> void drm_sched_fence_init(struct drm_sched_fence *fence,