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From:   Bartosz Golaszewski <bgolaszewski@baylibre.com>
Date:   Wed, 22 Sep 2021 12:18:05 +0200
Message-ID: <CAMpxmJVUTy5iOoTuDTY8-7z-brLJwkv_a82tU47ZXsJjM_Vp1A@mail.gmail.com>
Subject: Re: [PATCH V3 3/3] gpio: modepin: Add driver support for modepin GPIO controller
To:     Michal Simek <michal.simek@xilinx.com>
Cc:     Piyush Mehta <piyush.mehta@xilinx.com>,
        Arnd Bergmann <arnd@arndb.de>, Zou Wei <zou_wei@huawei.com>,
        Greg KH <gregkh@linuxfoundation.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        wendy.liang@xilinx.com, Nobuhiro Iwamatsu <iwamatsu@nigauri.org>,
        Rob Herring <robh+dt@kernel.org>, rajan.vaja@xilinx.com,
        linux-gpio <linux-gpio@vger.kernel.org>,
        linux-devicetree <devicetree@vger.kernel.org>,
        git <git@xilinx.com>, Srinivas Goud <sgoud@xilinx.com>,
        arm-soc <linux-arm-kernel@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Mon, Aug 23, 2021 at 10:14 AM Michal Simek <michal.simek@xilinx.com> wrote:
>
> Hi Bart,
>
> On 8/23/21 10:02 AM, Bartosz Golaszewski wrote:
> > On Wed, Aug 18, 2021 at 10:11 AM Piyush Mehta <piyush.mehta@xilinx.com> wrote:
> >>
> >> This patch adds driver support for the zynqmp modepin GPIO controller.
> >> GPIO modepin driver set and get the value and status of the PS_MODE pin,
> >> based on device-tree pin configuration. These four mode pins are
> >> configurable as input/output. The mode pin has a control register, which
> >> have lower four-bits [0:3] are configurable as input/output, next four-bits
> >> can be used for reading the data  as input[4:7], and next setting the
> >> output pin state output[8:11].
> >>
> >> Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
> >> Acked-by: Michal Simek <michal.simek@xilinx.com>
> >> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> >> ---
> >
> > Which tree should this go through?
>
> I would prefer to go this via gpio tree.
>
> Thanks,
> Michal

Sure, just make sure to get an Ack from Rob Herring on the DT bindings.

Bart