Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp827340pxb; Wed, 22 Sep 2021 13:59:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQ9EO/zU+6+sJDk3X3gNR4rc2aDcTUb763GsrW5nVOgyxUZ03jKpybZqX+OiDHQjCdri6+ X-Received: by 2002:a6b:b7d6:: with SMTP id h205mr877296iof.60.1632344352626; Wed, 22 Sep 2021 13:59:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632344352; cv=none; d=google.com; s=arc-20160816; b=BGq5X/bm9HG/WnG+ceeY4PdPWH8OkT5PnsN6kplem0R6ivLixcAqg/S4JbSPfVMgW0 gnsGOQ9Rs6LHHY5jfkvHSOj0Xy+17vxwv8EP1wI4EwDpBPC3CfeWjZeWZfB3WkcZVvMS dPKMedM+1TGYXKIcWtIehwZmdj6AwzgpOarCcoYa3EQdgK9WqUf0We24cd2m8a5dm79S i9l3fZBdFO+fYGTsWz2q5K2DdeX1je7Lua7AttgFdGKflpF91/u2FJZZCaHIXCtbrSy/ XJkDRiftXoWYrFf4WHFMVDlhtT7XLOpiij83YMiUba0Up2QI4NugNrCXH3R5C+etPFDI /MyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=6RL28FsvtQQ1VCoOvXApATqii1tMJtUVbIdxzS4Kq9E=; b=OkdIgjaG5eowKyMG0wkt5csiZsQhQZQunQHaCP8ySzGsAZheHuQ/8L/JZw4JlGZQLA 6TsYL+jVwNWhj0+xnEX23XH551fr+lS/ZpQiyzPSaLUWckXoCwkKnSTOfwkDuBxyfuhY YDfilMSZwVxxWBhX2M6Nd6K3i8V9Eyg5o4L0VY7fVrDOmiIgvT5lJZRIyqA7CXqjLkDn NsWj8IIW70n5B37tuh/fwrqXprWoGZm4sxsvVMjv3zjGlnozR5hwJh7/fisF2C10dK5D N00vutvHwpZLkRkvYJ6SJxkTEjH+ZVo+0on7am5DkGtiWgqND/Gx+UEN4kYcFZqTkWrv d6cQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y10si3911735ion.41.2021.09.22.13.59.01; Wed, 22 Sep 2021 13:59:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237831AbhIVU7A (ORCPT + 99 others); Wed, 22 Sep 2021 16:59:00 -0400 Received: from aposti.net ([89.234.176.197]:47320 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237783AbhIVU6w (ORCPT ); Wed, 22 Sep 2021 16:58:52 -0400 From: Paul Cercueil To: David Airlie , Daniel Vetter Cc: linux-mips@vger.kernel.org, list@opendingux.net, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH v3 4/6] drm/ingenic: Set DMA descriptor chain register when starting CRTC Date: Wed, 22 Sep 2021 21:55:53 +0100 Message-Id: <20210922205555.496871-5-paul@crapouillou.net> In-Reply-To: <20210922205555.496871-1-paul@crapouillou.net> References: <20210922205555.496871-1-paul@crapouillou.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setting the DMA descriptor chain register in the probe function has been fine until now, because we only ever had one descriptor per foreground. As the driver will soon have real descriptor chains, and the DMA descriptor chain register updates itself to point to the current descriptor being processed, this register needs to be reset after a full modeset to point to the first descriptor of the chain. Signed-off-by: Paul Cercueil --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 5dbeca0f8f37..cbc76cede99e 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -186,6 +186,10 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, regmap_write(priv->map, JZ_REG_LCD_STATE, 0); + /* Set address of our DMA descriptor chain */ + regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, 0)); + regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_ENABLE); -- 2.33.0