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Date:   Thu, 23 Sep 2021 02:40:07 +0300
From:   Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Kieran Bingham <kieran.bingham@ideasonboard.com>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display
 output
Message-ID: <YUu+14+9DnQZM7SE@pendragon.ideasonboard.com>
References: <20210901235330.1611086-1-kieran.bingham@ideasonboard.com>
 <20210901235330.1611086-4-kieran.bingham@ideasonboard.com>
 <CAMuHMdU5WzvdfeSqEESt0r7_7XX0Mc9jRNGCBHLtt_JCMCWZyw@mail.gmail.com>
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Hello,

On Tue, Sep 21, 2021 at 05:59:24PM +0200, Geert Uytterhoeven wrote:
> On Thu, Sep 2, 2021 at 1:53 AM Kieran Bingham wrote:
> > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> >
> > Provide the display output using the sn65dsi86 MIPI DSI bridge.
> >
> > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
> > @@ -66,6 +66,15 @@ memory@700000000 {
> >                 reg = <0x7 0x00000000 0x0 0x80000000>;
> >         };
> >
> > +       reg_1p2v: regulator-1p2v {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "fixed-1.2V";
> > +               regulator-min-microvolt = <1800000>;
> > +               regulator-max-microvolt = <1800000>;
> > +               regulator-boot-on;
> > +               regulator-always-on;
> > +       };
> > +
> >         reg_1p8v: regulator-1p8v {
> >                 compatible = "regulator-fixed";
> >                 regulator-name = "fixed-1.8V";
> > @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v {
> >                 regulator-boot-on;
> >                 regulator-always-on;
> >         };
> > +
> > +       mini-dp-con {
> > +               compatible = "dp-connector";
> > +               label = "CN5";
> > +               type = "mini";
> > +
> > +               port {
> > +                       mini_dp_con_in: endpoint {
> > +                               remote-endpoint = <&sn65dsi86_out>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       sn65dsi86_refclk: sn65dsi86-refclk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <38400000>;
> > +       };
> > +};
> > +
> > +&dsi0 {
> > +       status = "okay";
> > +
> > +       clocks = <&cpg CPG_MOD 415>,
> > +                <&cpg CPG_CORE R8A779A0_CLK_DSI>,
> > +                <&extal_clk>;
> > +       clock-names = "fck", "dsi", "extal";
> 
> Ah, that's where the third clock was hiding ;-)
> 
> Is this hardwired to extal, or board-specific?
> In case of the former, I think it should be moved to the .dtsi.

I think this is actually incorrect. The clock name, according to the
bindings, is "pll", and it's documented as a 16.66MHz PLL reference
clock. It comes from the CPG, but I'm not sure which clock it actually
is.

-- 
Regards,

Laurent Pinchart