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From:   "H.J. Lu" <hjl.tools@gmail.com>
Date:   Wed, 22 Sep 2021 17:15:06 -0700
Message-ID: <CAMe9rOp+_2LcMWcxxnJVH1CtQQT1Az1V2VW-dXA0_o0eM6iHdQ@mail.gmail.com>
Subject: Re: [RFC 0/9] Linear Address Masking enabling
To:     Dmitry Vyukov <dvyukov@google.com>
Cc:     "Zhang, Xiang1" <xiang1.zhang@intel.com>,
        "Kirill A. Shutemov" <kirill@shutemov.name>,
        "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "Lutomirski, Andy" <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        "the arch/x86 maintainers" <x86@kernel.org>,
        Andrey Ryabinin <aryabinin@virtuozzo.com>,
        Alexander Potapenko <glider@google.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>, Andi Kleen <ak@linux.intel.com>,
        Linux-MM <linux-mm@kvack.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "Carlos O'Donell" <carlos@redhat.com>,
        Marco Elver <elver@google.com>,
        Taras Madan <tarasmadan@google.com>
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On Wed, Sep 22, 2021 at 1:03 PM Dmitry Vyukov <dvyukov@google.com> wrote:
>
> On Wed, 22 Sept 2021 at 14:54, Dmitry Vyukov <dvyukov@google.com> wrote:
> >
> > On Wed, 22 Sept 2021 at 03:15, Zhang, Xiang1 <xiang1.zhang@intel.com> w=
rote:
> > >
> > > There are already in llvm.org.
> > > One of my old patch is https://reviews.llvm.org/D102472 which has bee=
n committed by https://reviews.llvm.org/D102901  and https://reviews.llvm.o=
rg/D109790
> >
> > Hi Xiang,
> >
> > Good sanitizer patches are upstream!
> >
> > Please help me to understand the status of other pieces (H.J. you
> > probably talked about this yesterday, but I wasn't able to build a
> > complete picture during the talk, I think it will be useful to have
> > this in written form).
> >
> > 1. The presentation mentions "GCC: enable memory tagging with LAM in
> > x86 codegen".
> > What exactly is needed? Isn't LAM transparent for codegen? What's the
> > status in gcc? Does a corresponding change need to be done in llvm?
> >
> > 2. "Enable LAM in binutils".
> > This is already upstream in binutils 2.36, right?
> >
> > 3. The mentioned glibc patch:
> > http://patchwork.ozlabs.org/project/glibc/patch/20210211173711.71736-1-=
hjl.tools@gmail.com/
> > Not upstream yet, targeting glibc 2.34.
>
> Do we need any support in other libc's, e.g. Android bionic?

Here is my tagged address API proposal:

https://sourceware.org/pipermail/libc-alpha/2021-August/130382.html

> > 4. "Avoid pointer operations incompatible with LAM. memmove: mask out
> > memory tags before comparing pointers".
> > Is this upstream? Where is the patch? Are there other similar patches?
> >
> > As a side note, regarding the memmove change: do we really need it?
> > Memory regions can overlap only if they come from the same
> > allocation/base object. If they come from different allocations, they
> > can't overlap (undefined behavior already).
> >
> > 5. Do we need any additional enabling changes in clang/llvm?
> >
> > 6. The kernel patches (this email thread) depend on the CET patches
> > (for the interface part only). And the CET patches is this, right?
> > https://lore.kernel.org/linux-doc/?q=3Dx86%2Fcet%2Fshstk
> >
> > 7. Do I miss anything else?
> >
> > H.J. please upload your slides here:
> > https://linuxplumbersconf.org/event/11/contributions/1010/
> > It would help with links and copy-pasting text.
> >
> > FTR here is the link to the Plumbers talk:
> > https://youtu.be/zUw0ZVXCwoM?t=3D10456
> >
> > Thank you
> >
> >
> > > BR
> > > Xiang
> > >
> > > -----Original Message-----
> > > From: H.J. Lu <hjl.tools@gmail.com>
> > > Sent: Wednesday, September 22, 2021 1:16 AM
> > > To: Dmitry Vyukov <dvyukov@google.com>
> > > Cc: Kirill A. Shutemov <kirill@shutemov.name>; Kirill A. Shutemov <ki=
rill.shutemov@linux.intel.com>; Dave Hansen <dave.hansen@linux.intel.com>; =
Lutomirski, Andy <luto@kernel.org>; Peter Zijlstra <peterz@infradead.org>; =
the arch/x86 maintainers <x86@kernel.org>; Andrey Ryabinin <aryabinin@virtu=
ozzo.com>; Alexander Potapenko <glider@google.com>; Catalin Marinas <catali=
n.marinas@arm.com>; Will Deacon <will@kernel.org>; Andi Kleen <ak@linux.int=
el.com>; Linux-MM <linux-mm@kvack.org>; LKML <linux-kernel@vger.kernel.org>=
; Carlos O'Donell <carlos@redhat.com>; Marco Elver <elver@google.com>; Tara=
s Madan <tarasmadan@google.com>; Zhang, Xiang1 <xiang1.zhang@intel.com>
> > > Subject: Re: [RFC 0/9] Linear Address Masking enabling
> > >
> > > On Tue, Sep 21, 2021 at 9:52 AM Dmitry Vyukov <dvyukov@google.com> wr=
ote:
> > > >
> > > > On Sun, 7 Feb 2021 at 15:11, Kirill A. Shutemov <kirill@shutemov.na=
me> wrote:
> > > > >
> > > > > On Sun, Feb 07, 2021 at 09:24:23AM +0100, Dmitry Vyukov wrote:
> > > > > > On Fri, Feb 5, 2021 at 4:16 PM Kirill A. Shutemov
> > > > > > <kirill.shutemov@linux.intel.com> wrote:
> > > > > > >
> > > > > > > Linear Address Masking[1] (LAM) modifies the checking that is
> > > > > > > applied to 64-bit linear addresses, allowing software to use =
of
> > > > > > > the untranslated address bits for metadata.
> > > > > > >
> > > > > > > The patchset brings support for LAM for userspace addresses.
> > > > > > >
> > > > > > > The most sensitive part of enabling is change in tlb.c, where
> > > > > > > CR3 flags get set. Please take a look that what I'm doing mak=
es sense.
> > > > > > >
> > > > > > > The patchset is RFC quality and the code requires more testin=
g
> > > > > > > before it can be applied.
> > > > > > >
> > > > > > > The userspace API is not finalized yet. The patchset extends =
API
> > > > > > > used by
> > > > > > > ARM64: PR_GET/SET_TAGGED_ADDR_CTRL. The API is adjusted to no=
t
> > > > > > > imply ARM
> > > > > > > TBI: it now allows to request a number of bits of metadata
> > > > > > > needed and report where these bits are located in the address=
.
> > > > > > >
> > > > > > > There's an alternative proposal[2] for the API based on Intel
> > > > > > > CET interface. Please let us know if you prefer one over anot=
her.
> > > > > > >
> > > > > > > The feature competes for bits with 5-level paging: LAM_U48 ma=
kes
> > > > > > > it impossible to map anything about 47-bits. The patchset mad=
e
> > > > > > > these capability mutually exclusive: whatever used first wins=
.
> > > > > > > LAM_U57 can be combined with mappings above 47-bits.
> > > > > > >
> > > > > > > I include QEMU patch in case if somebody wants to play with t=
he feature.
> > > > > >
> > > > > > Exciting! Do you plan to send the QEMU patch to QEMU?
> > > > >
> > > > > Sure. After more testing, once I'm sure it's conforming to the ha=
rdware.
> > > >
> > > > A follow up after H.J.'s LPC talk:
> > > > https://linuxplumbersconf.org/event/11/contributions/1010/
> > > > (also +Carlos)
> > > >
> > > > As far as I understood, this kernel series depends on the Intel CET=
 patches.
> > > >
> > > > Where are these compiler-rt patches that block gcc support?
> > >
> > > Hi Xiang,
> > >
> > > Please share your compiler-rt changes for LAM.
> > >
> > > --
> > > H.J.


--=20
H.J.