Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp311810pxb; Wed, 22 Sep 2021 23:57:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuhA4z6lhvSgby8DWerqNn3GSnuWj5v+nTdtFFAF1nVDHweYWM/7tu337WYikFIPuj/m7I X-Received: by 2002:a50:fa89:: with SMTP id w9mr3826367edr.113.1632380251612; Wed, 22 Sep 2021 23:57:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632380251; cv=none; d=google.com; s=arc-20160816; b=G+uFEEV28tn4LZvYM0BKklqMnuoQc6/k1Ds7pn8YrKqGM7pAvSu1IP93spW2rcdLl9 9pgHroYjrMIiUcDza6T6qvSvYCNQk/KbpfNRplTYRsFZKRnWfKEqsIgcE+J7tCAnVDkH /JqSNfOK7PukaExwVYyX3FWaOG3Er5Uve/kXSG9oQ7lBYyXFT+BIvBZ9b9PjCZw1QdPG IfrIhhlOOrP1PHCVCXfoYl1+QF0RBaXLOO3lGLD7Re/Zay9OfPtdrQD9NcUpsz8UrrPA v6xvVfrik3E3MpQp4Z/hSuARc9rOAuAfrtXp2If7SffDFqDKdaDyyhWK7B4LyHWhofKE Br5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N4fLW3GjiZK81aHwIFNX6SQcQ6QOSmBTc6L0mWZHJks=; b=0hb+LjHJqSAo+xQMs7pOqgfW85LHdncLl1ZLhvYKU5wT2vDgipRUdbl7b6l0ep80CZ DrQWTEDM3vjej3zdXItOb/eRodq0vUD8bSsRRzc0p2H2ghY/TcUvLtuySHGk1Vaa9Ba3 M4xQpIOuUGmYSoxNGDQ6U7C2HrYCqAAQQhQrwMk18KDwgW3XiuUyVQ6d6/FMOmJMo4Bz 9bmVBnK1gPj5Egf3KofOQNsyxcGUUFqchAbZ/nk1GDfZagG3bBPJTdVFJ5yvfc1btKlW j9UNC6Xz7MTwor/NSNo+7ntwpDjtjAu1IGaEQNoMs7ZnlZWks7Ugi0upaWzQBRdNrk7T J1fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@0x0f.com header.s=google header.b=S5u2ACy7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id jz21si5038689ejb.539.2021.09.22.23.57.06; Wed, 22 Sep 2021 23:57:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@0x0f.com header.s=google header.b=S5u2ACy7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239485AbhIWG5R (ORCPT + 99 others); Thu, 23 Sep 2021 02:57:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239482AbhIWG5P (ORCPT ); Thu, 23 Sep 2021 02:57:15 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30A04C061760 for ; Wed, 22 Sep 2021 23:55:44 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id g13-20020a17090a3c8d00b00196286963b9so6257392pjc.3 for ; Wed, 22 Sep 2021 23:55:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N4fLW3GjiZK81aHwIFNX6SQcQ6QOSmBTc6L0mWZHJks=; b=S5u2ACy7xH+pz5i0ZeHgjEotrZPmDkrGrAsAZFIPjV4ZlTD4gJpQ6kZmvRjo8x76xW 4JxKTTlc75Hgz4+6DKm1f++dR5tw6xyZ4zIEmQrMC++Z+TeL69hM+IfKGwDbaUAlqzuM W/+sVMobbMSJ7a+otzLN05ITrSX/uvrq/6voM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N4fLW3GjiZK81aHwIFNX6SQcQ6QOSmBTc6L0mWZHJks=; b=N7khJLWPvvXUtROr52FfHtHoS25sc9G7+09Qm8ioK7McQK31gX1Xs5jF2Yo3zkjIAy OFKjmpnLA+F1O+OMS8ym1+dHCLQjTJ5psJFTpvLJpb4ZCl5DOWYMPunO7wPs0Gz1msgI Axj+RlIL0c6Y+VkAUIpaXNQcc+JBxdI2tG3tkBE9R/wU6zkfrAcRaPpJEhBvQXaIum+o soqbkOQ0yFe0zU3LJklIk1n5SqaLIFZLjMDbslCzu+Nb33iORuKNhNvVsWnCAv1N/g5+ ApymcTSiFON79+HctYAmaLAFgM5Gs1qppogQXiiAir2bN3fDFLpZAhWS08Fsfkqto+Wp rk7A== X-Gm-Message-State: AOAM5303rBN5evhCn4WnZlJfMq5L3vUK9ZXA/nkW4kctkBOqxa6UaDv2 w2QYvZZWqnZMkPxoZeuKLg065g== X-Received: by 2002:a17:902:e793:b0:13b:9cae:5dcd with SMTP id cp19-20020a170902e79300b0013b9cae5dcdmr2587777plb.53.1632380143745; Wed, 22 Sep 2021 23:55:43 -0700 (PDT) Received: from shiro.work ([2400:4162:2428:2f01:7285:c2ff:fe8e:66d7]) by smtp.googlemail.com with ESMTPSA id e12sm1581888pgv.82.2021.09.22.23.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Sep 2021 23:55:43 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-leds@vger.kernel.org Cc: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, pavel@ucw.cz, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Daniel Palmer , Rob Herring Subject: [PATCH v2 02/11] dt-bindings: gpio: msc313: Add offsets for ssd20xd Date: Thu, 23 Sep 2021 15:54:51 +0900 Message-Id: <20210923065500.2284347-3-daniel@0x0f.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923065500.2284347-1-daniel@0x0f.com> References: <20210923065500.2284347-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the gpio offsets for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer Acked-by: Rob Herring Reviewed-by: Linus Walleij --- include/dt-bindings/gpio/msc313-gpio.h | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/include/dt-bindings/gpio/msc313-gpio.h b/include/dt-bindings/gpio/msc313-gpio.h index 2dd56683d3c1..5458c6580a02 100644 --- a/include/dt-bindings/gpio/msc313-gpio.h +++ b/include/dt-bindings/gpio/msc313-gpio.h @@ -50,4 +50,75 @@ #define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) #define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) +/* SSD20x */ +#define SSD20XD_GPIO_FUART 0 +#define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0) +#define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1) +#define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2) +#define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3) + +#define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1) +#define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0) +#define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1) +#define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2) +#define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3) +#define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4) +#define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5) + +#define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1) +#define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0) +#define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1) + +#define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1) +#define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0) +#define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1) + +#define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1) +#define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0) +#define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1) +#define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2) +#define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3) +#define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4) +#define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5) +#define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6) +#define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7) +#define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8) +#define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9) +#define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10) +#define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11) +#define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12) +#define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13) +#define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14) +#define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15) +#define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16) +#define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17) +#define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18) +#define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19) +#define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20) +#define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21) +#define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22) +#define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23) +#define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24) +#define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25) +#define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26) +#define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27) + +#define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1) +#define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0) +#define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1) +#define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2) +#define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3) +#define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4) +#define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5) +#define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6) +#define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7) +#define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8) +#define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9) +#define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10) +#define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11) +#define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12) +#define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13) +#define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14) +#define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15) + #endif /* _DT_BINDINGS_MSC313_GPIO_H */ -- 2.33.0