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From:   Anup Patel <anup@brainfault.org>
Date:   Thu, 23 Sep 2021 16:06:21 +0530
Message-ID: <CAAhSdy33=4AWaYWT8P5iCrvTcoOEgwm1NgcxJCq53Pp6zzNruQ@mail.gmail.com>
Subject: Re: [PATCH] riscv: Add RISC-V svpbmt extension
To:     Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc:     Nick Kossifidis <mick@ics.forth.gr>, Guo Ren <guoren@kernel.org>,
        Anup Patel <anup.patel@wdc.com>,
        Atish Patra <atish.patra@wdc.com>,
        Palmer Dabbelt <palmerdabbelt@google.com>,
        =?UTF-8?Q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu>,
        Christoph Hellwig <hch@lst.de>,
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        Drew Fustini <drew@beagleboard.org>,
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        taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
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On Thu, Sep 23, 2021 at 3:38 PM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> On Thu, 23 Sept 2021 at 11:48, Nick Kossifidis <mick@ics.forth.gr> wrote:
> >
> > =CE=A3=CF=84=CE=B9=CF=82 2021-09-23 12:42, Nick Kossifidis =CE=AD=CE=B3=
=CF=81=CE=B1=CF=88=CE=B5:
> > > =CE=A3=CF=84=CE=B9=CF=82 2021-09-23 12:37, Anup Patel =CE=AD=CE=B3=CF=
=81=CE=B1=CF=88=CE=B5:
> > >> On Thu, Sep 23, 2021 at 2:55 PM Nick Kossifidis <mick@ics.forth.gr>
> > >> wrote:
> > >>>
> > >>> Hello Guo,
> > >>>
> > >>> =CE=A3=CF=84=CE=B9=CF=82 2021-09-23 10:27, guoren@kernel.org =CE=AD=
=CE=B3=CF=81=CE=B1=CF=88=CE=B5:
> > >>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > >>> b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > >>> index e534f6a7cfa1..1825cd8db0de 100644
> > >>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > >>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > >>> @@ -56,7 +56,9 @@ properties:
> > >>>       enum:
> > >>>         - riscv,sv32
> > >>>         - riscv,sv39
> > >>> +      - riscv,sv39,svpbmt
> > >>>         - riscv,sv48
> > >>> +      - riscv,sv48,svpbmt
> > >>>         - riscv,none
> > >>>
> > >>> Isn't svpbmt orthogonal to the mmu type ? It's a functionality that
> > >>> can
> > >>> be present on either sv39/48/57 so why not have another "svpbmt"
> > >>> property directly on the cpu node ?
> > >>
> > >> Actually, "mmu-type" would be a good place because it's page based
> > >> memory attribute and paging can't exist without mmu translation mode=
.
> > >>
> > >> Also, "svpmbt" is indeed a CPU property so has to be feature
> > >> individual
> > >> CPU node. Hypothetically, a heterogeneous system is possible where
> > >> some CPUs have "svpmbt" and some CPUs don't have "svpmbt". For
> > >> example, a future FUxxx SoC might have a E-core and few S-cores
> > >> where S-cores have Svpmbt whereas E-core does not have Svpmbt
> > >> because it's an embedded core.
> > >>
> > >
> > > I should say cpuX node, not the root /cpu node. We can have an svpbmt
> > > property in the same way we have an mmu-type property.
> > >
> >
> > I'm also thinking of future mmu-related extensions, e.g. what about
> > svnapot ? Should we have mmu-type be riscv,sv39,svnapot and e.g.
> > riscv.sv39,svpbmt,svnapot ? It'll become messy.
>
> How if we expand this to a mmu subnode in cpu@x and add a booleans for
> adornments like svnapot and svpbmt?
>
> The older mmu-type could then treated to indicate a mmu w/o any adornment=
s
> specified.  I am aware that this generates an additional parsing-path
> that will be
> maintained, but it will allow future properties to be grouped.
>
> This could like like the following:
>
>   cpu@0 {
>     ...
>     mmu {
>        type =3D "riscv,sv39";
>        supports-svpbmt;
>     }
>     ...
>   }

This is better but we will have to support the old "mmu-type" DT
property as well because we can't break compatibility in DT bindings.

Regards,
Anup