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Thu, 23 Sep 2021 12:05:29 +0000 From: "Tian, Kevin" To: Jason Gunthorpe , Jean-Philippe Brucker CC: Alex Williamson , "Liu, Yi L" , "hch@lst.de" , "jasowang@redhat.com" , "joro@8bytes.org" , "parav@mellanox.com" , "lkml@metux.net" , "pbonzini@redhat.com" , "lushenming@huawei.com" , "eric.auger@redhat.com" , "corbet@lwn.net" , "Raj, Ashok" , "yi.l.liu@linux.intel.com" , "Tian, Jun J" , "Wu, Hao" , "Jiang, Dave" , "jacob.jun.pan@linux.intel.com" , "kwankhede@nvidia.com" , "robin.murphy@arm.com" , "kvm@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "dwmw2@infradead.org" , "linux-kernel@vger.kernel.org" , "baolu.lu@linux.intel.com" , "david@gibson.dropbear.id.au" , "nicolinc@nvidia.com" Subject: RE: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO Thread-Topic: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO Thread-Index: AQHXrSGNbNtRgavabUSKJjvt8l12BauwlhaAgAAouwCAACufAIAAgyUAgAAUFACAAAdkgA== Date: Thu, 23 Sep 2021 12:05:29 +0000 Message-ID: References: <20210919063848.1476776-1-yi.l.liu@intel.com> <20210919063848.1476776-11-yi.l.liu@intel.com> <20210922152407.1bfa6ff7.alex.williamson@redhat.com> <20210922234954.GB964074@nvidia.com> <20210923112716.GE964074@nvidia.com> In-Reply-To: <20210923112716.GE964074@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5433.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5e57bd55-ef5f-4acf-a315-08d97e8a6fe9 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Sep 2021 12:05:29.6212 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ewJC8j3gCaD6GlJPggzbbCk+p4pxK0/j+1GdWqKAtpJTbR+0w97HDNuyyBGaWKHhiN0IvOarW6ops+ncPsfUuw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR11MB2595 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jason Gunthorpe > Sent: Thursday, September 23, 2021 7:27 PM >=20 > On Thu, Sep 23, 2021 at 11:15:24AM +0100, Jean-Philippe Brucker wrote: >=20 > > So we can only tell userspace "No_snoop is not supported" (provided we > > even want to allow them to enable No_snoop). Users in control of stage-= 1 > > tables can create non-cacheable mappings through MAIR attributes. >=20 > My point is that ARM is using IOMMU_CACHE to control the overall > cachability of the DMA >=20 > ie not specifying IOMMU_CACHE requires using the arch specific DMA > cache flushers. >=20 > Intel never uses arch specifc DMA cache flushers, and instead is > abusing IOMMU_CACHE to mean IOMMU_BLOCK_NO_SNOOP on DMA that > is always > cachable. it uses IOMMU_CACHE to force all DMAs to snoop, including those which has non_snoop flag and wouldn't snoop cache if iommu is disabled. Nothing is blocked. but why do you call it abuse? IOMMU_CACHE was first introduced for Intel platform: commit 9cf0669746be19a4906a6c48920060bcf54c708b Author: Sheng Yang Date: Wed Mar 18 15:33:07 2009 +0800 intel-iommu: VT-d page table to support snooping control bit The user can request to enable snooping control through VT-d page table= . Signed-off-by: Sheng Yang Signed-off-by: David Woodhouse >=20 > These are different things and need different bits. Since the ARM path > has a lot more code supporting it, I'd suggest Intel should change > their code to use IOMMU_BLOCK_NO_SNOOP and abandon IOMMU_CACHE. I didn't fully get this point. The end result is same, i.e. making the DMA cache-coherent when IOMMU_CACHE is set. Or if you help define the behavior of IOMMU_CACHE, what will you define now? >=20 > Which clarifies what to do here as uAPI - these things need to have > different bits and Intel's should still have NO SNOOP in the > name. What the no-snoop bit is called on other busses can be clarified > in comments if that case ever arises. >=20 > Jason