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From:   "Joshi, Mukul" <Mukul.Joshi@amd.com>
To:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
CC:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
        "x86@kernel.org" <x86@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        "mchehab@kernel.org" <mchehab@kernel.org>,
        "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCHv3 2/2] drm/amdgpu: Register MCE notifier for Aldebaran RAS
Thread-Topic: [PATCHv3 2/2] drm/amdgpu: Register MCE notifier for Aldebaran
 RAS
Thread-Index: AQHXr+ktpJldbvXsiEi/xMi8ZoJNQKuxrumAgAAF1YA=
Date:   Thu, 23 Sep 2021 15:30:55 +0000
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References: <20210913021311.12896-2-mukul.joshi@amd.com>
 <20210922193620.15925-1-mukul.joshi@amd.com> <YUyPM7VfYFG/PJmu@yaz-ubuntu>
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[AMD Official Use Only]


> -----Original Message-----
> From: Ghannam, Yazen <Yazen.Ghannam@amd.com>
> Sent: Thursday, September 23, 2021 10:29 AM
> To: Joshi, Mukul <Mukul.Joshi@amd.com>
> Cc: linux-edac@vger.kernel.org; x86@kernel.org; linux-kernel@vger.kernel.=
org;
> bp@alien8.de; mingo@redhat.com; mchehab@kernel.org; amd-
> gfx@lists.freedesktop.org
> Subject: Re: [PATCHv3 2/2] drm/amdgpu: Register MCE notifier for Aldebara=
n
> RAS
>=20
> On Wed, Sep 22, 2021 at 03:36:20PM -0400, Mukul Joshi wrote:
> > On Aldebaran, GPU driver will handle bad page retirement even though
> > UMC is host managed. As a result, register a bad page retirement
> > handler on the mce notifier chain to retire bad pages on Aldebaran.
> >
>=20
> I think this should state that the driver will do page retirement for GPU=
-managed
> memory. As written, it implies that the driver do page retirement in gene=
ral for
> the system.
>=20
ACK. I will update the description.
> ...
>=20
> > +
> > +static int amdgpu_bad_page_notifier(struct notifier_block *nb,
> > +				    unsigned long val, void *data) {
> > +	struct mce *m =3D (struct mce *)data;
> > +	struct amdgpu_device *adev =3D NULL;
> > +	uint32_t gpu_id =3D 0;
> > +	uint32_t umc_inst =3D 0;
> > +	uint32_t ch_inst, channel_index =3D 0;
> > +	struct ras_err_data err_data =3D {0, 0, 0, NULL};
> > +	struct eeprom_table_record err_rec;
> > +	uint64_t retired_page;
> > +
> > +	/*
> > +	 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
> > +	 * and error occurred in DramECC (Extended error code =3D 0) then onl=
y
> > +	 * process the error, else bail out.
> > +	 */
> > +	if (!m || !((smca_get_bank_type(m->bank) =3D=3D SMCA_UMC_V2) &&
> > +		    (XEC(m->status, 0x1f) =3D=3D 0x0)))
>=20
> The MCA_STATUS[ErrorCodeExt] field is bits [21:16], so the mask should be
> 0x3f.

Ack. Thanks for catching this.
>=20
> > +		return NOTIFY_DONE;
> > +
> > +	/*
> > +	 * If it is correctable error, return.
> > +	 */
> > +	if (mce_is_correctable(m))
> > +		return NOTIFY_OK;
>=20
> Shouldn't this be "NOTIFY_DONE" if "don't care" about this error?

The thinking is we want to stop calling further consumers since it's a corr=
ectable error in GPU UMC and we are not taking any action about the correct=
able errors.

Thanks,
Mukul

>=20
> Thanks,
> Yazen