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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id i1sm1583036ooo.15.2021.09.23.13.31.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Sep 2021 13:31:01 -0700 (PDT) From: Bjorn Andersson To: Shaik Sajida Bhanu , ulf.hansson@linaro.org, adrian.hunter@intel.com, robh+dt@kernel.org Cc: rampraka@codeaurora.org, sartgarg@codeaurora.org, nitirawa@codeaurora.org, sayalil@codeaurora.org, cang@codeaurora.org, linux-mmc@vger.kernel.org, agross@kernel.org, devicetree@vger.kernel.org, stummala@codeaurora.org, pragalla@codeaurora.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, asutoshd@codeaurora.org Subject: Re: (subset) [PATCH V1] arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC Date: Thu, 23 Sep 2021 15:30:59 -0500 Message-Id: <163242893971.825761.9292228692666120286.b4-ty@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <1629132650-26277-1-git-send-email-sbhanu@codeaurora.org> References: <1629132650-26277-1-git-send-email-sbhanu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 16 Aug 2021 22:20:50 +0530, Shaik Sajida Bhanu wrote: > The current drive strength values are not sufficient on non discrete > boards and this leads to CRC errors during switching to HS400 enhanced > strobe mode. > > Hardware simulation results on non discrete boards shows up that use the > maximum drive strength values for data and command lines could helps > in avoiding these CRC errors. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC commit: 752432e40e8f0d02d0af07cce2d6d4b250be11ef Best regards, -- Bjorn Andersson