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From:   Tao Zhang <quic_taozha@quicinc.com>
To:     Mathieu Poirier <mathieu.poirier@linaro.org>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>
CC:     Tao Zhang <quic_taozha@quicinc.com>,
        Mike Leach <mike.leach@linaro.org>,
        Leo Yan <leo.yan@linaro.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        <coresight@lists.linaro.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        Tingwei Zhang <quic_tingweiz@quicinc.com>,
        Mao Jinlong <quic_jinlmao@quicinc.com>,
        Yuanfang Zhang <quic_yuanfang@quicinc.com>
Subject: [PATCH v2 0/2] Add Coresight support for RB5 board
Date:   Fri, 24 Sep 2021 18:06:19 +0800
Message-ID: <1632477981-13632-1-git-send-email-quic_taozha@quicinc.com>
MIME-Version: 1.0
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This series adds Coresight support for SM8250 Soc on RB5 board.
It is composed of two elements.
a) Add ETM PID for Kryo-5XX.
b) Add coresight support to DTS for RB5.

Changes since V2:
- Add the comment "Cortex-A77" for Kryo-5XX ETM PID.
- Correct the errors in the patch "Add Coresight support for RB5
board" v1 version, and the adsp-related configuration should not
be deleted.

Changes since V1:
- Add ETM PID for Kryo-5XX.
- Add coresight supoort to device tree for RB5. ETM verification
and use of Coresight components need Coresight support in device
tree. Since the ETR sink needs SMMU support, and SMMU has not
been enabled on RB5. ETR is not added to this patch, and it will
be added once SMMU is enabled on RB5. ETF sink has been added to
the device tree for RB5.

This series applies to coresight/next
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

Tao Zhang (2):
  coresight: etm4x: Add ETM PID for Kryo-5XX
  arm64: dts: qcom: sm8250: Add Coresight support

 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts      | 442 +++++++++++++++++-
 .../coresight/coresight-etm4x-core.c          |   1 +
 2 files changed, 439 insertions(+), 4 deletions(-)

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