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Fri, 24 Sep 2021 03:09:44 -0700 Envelope-to: git@xilinx.com, arnd@arndb.de, saikrishna12468@gmail.com, broonie@kernel.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, iwamatsu@nigauri.org, p.yadav@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Received: from [172.23.63.68] (port=40686 helo=xhdvnc208.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mTi9H-0003Zq-FL; Fri, 24 Sep 2021 03:09:43 -0700 Received: by xhdvnc208.xilinx.com (Postfix, from userid 14964) id 48318207A4; Fri, 24 Sep 2021 15:39:16 +0530 (IST) From: Sai Krishna Potthuri To: Mark Brown , Rob Herring , Pratyush Yadav , Michal Simek , "Greg Kroah-Hartman" CC: , , , , , , Arnd Bergmann , Nobuhiro Iwamatsu , Sai Krishna Potthuri Subject: [PATCH 2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI Date: Fri, 24 Sep 2021 15:37:09 +0530 Message-ID: <1632478031-12242-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1632478031-12242-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> References: <1632478031-12242-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 650c71be-8b36-4da1-cd71-08d97f437763 X-MS-TrafficTypeDiagnostic: SA0PR02MB7274: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2021 10:09:59.0802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 650c71be-8b36-4da1-cd71-08d97f437763 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT062.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7274 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add new compatible to support Cadence Octal SPI(OSPI) controller on Xilinx Versal SoCs, also add power-domains property to the properties list and marked as required for Xilinx Versal OSPI compatible. Signed-off-by: Sai Krishna Potthuri --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 0e7087cc8bf9..ca155abbda7a 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -11,6 +11,14 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: xlnx,versal-ospi-1.0 + then: + required: + - power-domains properties: compatible: @@ -20,6 +28,7 @@ properties: - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi + - xlnx,versal-ospi-1.0 - const: cdns,qspi-nor - const: cdns,qspi-nor @@ -65,6 +74,9 @@ properties: data rather than the QSPI clock. Make sure that QSPI return clock is populated on the board before using this property. + power-domains: + maxItems: 1 + resets: maxItems: 2 -- 2.17.1