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[23.128.96.18]) by mx.google.com with ESMTP id p5si1992659ejj.74.2021.09.24.23.41.05; Fri, 24 Sep 2021 23:41:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=c8xPfPI4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232695AbhIXXzy (ORCPT + 99 others); Fri, 24 Sep 2021 19:55:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238839AbhIXXzx (ORCPT ); Fri, 24 Sep 2021 19:55:53 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6A09C06161E for ; Fri, 24 Sep 2021 16:54:19 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id me1so8061135pjb.4 for ; Fri, 24 Sep 2021 16:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DBB9PqXKAn7JtQopDAKE4raqjGwkNHbNRgTQPsWiL3c=; b=c8xPfPI4duwa9I6vi1raT4puwIuiPfSC9BaLtdCDky6A16i7hlE/yhNdtg6JQqHch2 KSdSuwDukV9o81R2JCS45+58QJo8XdKvdyb2UDVXLB20f2e0KPY8yr24nLkx9ijWsoYI pHRdMsUz0/sDYf073T7mSHx8niFL8K28khLIs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DBB9PqXKAn7JtQopDAKE4raqjGwkNHbNRgTQPsWiL3c=; b=vWFGR3eX71s0A9FfEy1pRghgQi7kgYnGVuNwai2u6v11v0RUPRhr/r+KH02Ifi0pKw CfdEA0fiQL+YNpd9tuoFrhypnu/wC854Z0M8rf5VI+upjkZWwTO3RRpgss7ypovYTON+ xxF1TsQWsZkqTIK3M7B0tWhltOMxbA9SjalJdpppIz+eYU3kpoGNvMLXonBaPhp13XFT tvOWIl0lDhMmO6iQjwr2VQi9nWkitJ0zs2lwwAoruPfWaJ8exId7xA4nl0Q1kLjlxGOp NRlOatZELqPVkG41xaoicUpHoHxDsMG7V5WbQgruEIUJLAUP0je6tgJJjBnxR3OG4Hi+ 7I9Q== X-Gm-Message-State: AOAM5310ffllJpkx7dxRTE/AnNGre/gq3YMprn87afxgN2ivnnUy9p62 0tlOsujoQKXkgPt33TRzgoXuSV/W3ix6Lg== X-Received: by 2002:a17:903:102:b0:13a:66a8:f28 with SMTP id y2-20020a170903010200b0013a66a80f28mr11615283plc.62.1632527658718; Fri, 24 Sep 2021 16:54:18 -0700 (PDT) Received: from philipchen.mtv.corp.google.com ([2620:15c:202:201:79e9:3064:a6e8:f955]) by smtp.gmail.com with ESMTPSA id d63sm12989406pjk.17.2021.09.24.16.54.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Sep 2021 16:54:18 -0700 (PDT) From: Philip Chen To: LKML Cc: dianders@chromium.org, swboyd@chromium.org, Philip Chen , Andy Gross , Bjorn Andersson , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH] arm64: dts: sc7180: Factor out ti-sn65dsi86 support Date: Fri, 24 Sep 2021 16:54:13 -0700 Message-Id: <20210924165322.1.Ib7e63ae17e827ce0636a09d5dec9796043e4f80a@changeid> X-Mailer: git-send-email 2.33.0.685.g46640cef36-goog MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Factor out ti-sn65dsi86 edp bridge as a separate dts fragment. This helps us introduce the second source edp bridge later. Signed-off-by: Philip Chen --- .../boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 + .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 1 + .../boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 1 + .../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 1 + .../dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 87 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 81 ----------------- 6 files changed, 91 insertions(+), 81 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index a758e4d22612..1d13fba3bd2f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -11,6 +11,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" /* Deleted nodes from trogdor.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 00535aaa43c9..27b26a782af9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -11,6 +11,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index a246dbd74cc1..e7c7cad14989 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -11,6 +11,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 2b522f9e0d8f..457c25499863 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -13,6 +13,7 @@ ap_h1_spi: &spi0 {}; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { model = "Google Trogdor (rev1+)"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi new file mode 100644 index 000000000000..7b1034a5a8e9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for the boards with TI sn65dsi86 edp bridge + * + * Copyright 2021 Google LLC. + */ + +&dsi0_out { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <0 1 2 3>; +}; + +&edp_brij_i2c { + sn65dsi86_bridge: bridge@2d { + compatible = "ti,sn65dsi86"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&pp1800_edp_vpll>; + vccio-supply = <&pp1800_brij_vccio>; + vcca-supply = <&pp1200_brij>; + vcc-supply = <&pp1200_brij>; + + clocks = <&rpmhcc RPMH_LN_BB_CLK3>; + clock-names = "refclk"; + + no-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + + aux-bus { + panel: panel { + /* Compatible will be filled in per-board */ + power-supply = <&pp3300_dx_edp>; + backlight = <&backlight>; + hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + }; +}; + +&tlmm { + edp_brij_irq: edp-brij-irq { + pinmux { + pins = "gpio11"; + function = "gpio"; + }; + + pinconf { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 0f2b3c00e434..5ad3f15652d5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -602,15 +602,6 @@ &camcc { &dsi0 { status = "okay"; vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; }; &dsi_phy { @@ -621,65 +612,6 @@ &dsi_phy { edp_brij_i2c: &i2c2 { status = "okay"; clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&tlmm>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&pp1800_edp_vpll>; - vccio-supply = <&pp1800_brij_vccio>; - vcca-supply = <&pp1200_brij>; - vcc-supply = <&pp1200_brij>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK3>; - clock-names = "refclk"; - - no-hpd; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - - aux-bus { - panel: panel { - /* Compatible will be filled in per-board */ - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; - }; }; ap_sar_sensor_i2c: &i2c5 { @@ -1245,19 +1177,6 @@ pinconf { }; }; - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio11"; - function = "gpio"; - }; - - pinconf { - pins = "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; - }; - en_pp3300_codec: en-pp3300-codec { pinmux { pins = "gpio83"; -- 2.33.0.685.g46640cef36-goog