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[23.128.96.18]) by mx.google.com with ESMTP id nc14si17599003ejc.445.2021.09.26.21.29.29; Sun, 26 Sep 2021 21:30:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=HZByLbb8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232075AbhI0E2Z (ORCPT + 99 others); Mon, 27 Sep 2021 00:28:25 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:24935 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231193AbhI0E2Y (ORCPT ); Mon, 27 Sep 2021 00:28:24 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1632716807; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=U7xwWG86NJbZVo9kJK4fvbMP5O7Q8h2IyIEICsOkjnA=; b=HZByLbb8yEIJpQyopFH4+qnQHLjJw0J3tt72XyULM1KiDImNgUXwkC0SUFLe821FIpjfSzxB WnDKiXb/vlaxllSpqyKvMgJMAkfMHy0MEpOB9GBL2+vEpyUI1aud8ay9fPIUPNg+SkbCeOBS us+pQ2fd74b5vihk9ULuTW+S5iE= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-east-1.postgun.com with SMTP id 615148001abbf21d3478e028 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 27 Sep 2021 04:26:40 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9BF9AC4361A; Mon, 27 Sep 2021 04:26:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id B3177C4338F; Mon, 27 Sep 2021 04:26:38 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 27 Sep 2021 09:56:38 +0530 From: Sai Prakash Ranjan To: Tao Zhang Cc: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Leach , Leo Yan , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Tingwei Zhang , Mao Jinlong , Yuanfang Zhang Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support In-Reply-To: <1632710581-11896-1-git-send-email-quic_taozha@quicinc.com> References: <1632710581-11896-1-git-send-email-quic_taozha@quicinc.com> Message-ID: <8ff1838f88670cc401a35dc43cc43feb@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Tao, On 2021-09-27 08:13, Tao Zhang wrote: > Add the basic coresight components found on Qualcomm SM8250 Soc. The > basic coresight components include ETF, ETMs,STM and the related > funnels. > ETM verification and use of Coresight components need Coresight > support in this device tree. Since the ETR sink needs SMMU support, > and SMMU has not been enabled on RB5. ETR is not added to this patch, > and it will be added once SMMU is enabled on RB5. ETF sink has been > added to the device tree for RB5. > RB5 board is based on SM8250 SoC and coresight is a SoC level IP (won't change per board, although can be disabled per board) and as such these coresight dt nodes should be in sm8250.dtsi (please look at other examples in SM8150/SC7180/SC7280). Similarly SMMU support is not per board (RB5), it's already supported for SM8250 long time back (check for apps_smmu in sm8250.dtsi), so you can add ETR support when you post v3 (note this patch which you have posted should have been v3 as v2 was your previous version). You can just post one patch with the coresight dt entries as the ETM driver patch is already queued by Suzuki in coresight tree. You can use the following qcom tree [1] when posting DT for QCOM devices (branch: for-next), also please remember to *sort the nodes by address*. [1] https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/?h=for-next Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation