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From:   Stefan Riedmueller <s.riedmueller@phytec.de>
To:     Abel Vesa <abel.vesa@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>
Cc:     Stefan Riedmueller <s.riedmueller@phytec.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/2] clk: imx: imx6ul: Move csi_sel mux to correct base register
Date:   Mon, 27 Sep 2021 09:28:56 +0200
Message-Id: <20210927072857.3940880-1-s.riedmueller@phytec.de>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

The csi=5Fsel mux register is located in the CCM register base and not the
CCM=5FANALOG register base. So move it to the correct position in code.

Otherwise changing the parent of the csi clock can lead to a complete
system failure due to the CCM=5FANALOG=5FPLL=5FSYS=5FTOG register being fal=
sely
modified.

Also remove the SET=5FRATE=5FPARENT flag since one possible supply for the
csi=5Fsel mux is the system PLL which we don't want to modify.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
No changes in v2.
---
 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 5dbb6a937732..206e4c43f68f 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -161,7 +161,6 @@ static void =5F=5Finit imx6ul=5Fclocks=5Finit(struct de=
vice=5Fnode *ccm=5Fnode)
 	hws[IMX6UL=5FPLL5=5FBYPASS] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("pll5=5Fbypa=
ss", base + 0xa0, 16, 1, pll5=5Fbypass=5Fsels, ARRAY=5FSIZE(pll5=5Fbypass=
=5Fsels), CLK=5FSET=5FRATE=5FPARENT);
 	hws[IMX6UL=5FPLL6=5FBYPASS] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("pll6=5Fbypa=
ss", base + 0xe0, 16, 1, pll6=5Fbypass=5Fsels, ARRAY=5FSIZE(pll6=5Fbypass=
=5Fsels), CLK=5FSET=5FRATE=5FPARENT);
 	hws[IMX6UL=5FPLL7=5FBYPASS] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("pll7=5Fbypa=
ss", base + 0x20, 16, 1, pll7=5Fbypass=5Fsels, ARRAY=5FSIZE(pll7=5Fbypass=
=5Fsels), CLK=5FSET=5FRATE=5FPARENT);
-	hws[IMX6UL=5FCLK=5FCSI=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("csi=5Fsel=
", base + 0x3c, 9, 2, csi=5Fsels, ARRAY=5FSIZE(csi=5Fsels), CLK=5FSET=5FRAT=
E=5FPARENT);
=20
 	/* Do not bypass PLLs initially */
 	clk=5Fset=5Fparent(hws[IMX6UL=5FPLL1=5FBYPASS]->clk, hws[IMX6UL=5FCLK=5FP=
LL1]->clk);
@@ -270,6 +269,7 @@ static void =5F=5Finit imx6ul=5Fclocks=5Finit(struct de=
vice=5Fnode *ccm=5Fnode)
 	hws[IMX6UL=5FCLK=5FECSPI=5FSEL]	  =3D imx=5Fclk=5Fhw=5Fmux("ecspi=5Fsel",=
	base + 0x38, 18, 1, ecspi=5Fsels, ARRAY=5FSIZE(ecspi=5Fsels));
 	hws[IMX6UL=5FCLK=5FLCDIF=5FPRE=5FSEL]	  =3D imx=5Fclk=5Fhw=5Fmux=5Fflags(=
"lcdif=5Fpre=5Fsel", base + 0x38, 15, 3, lcdif=5Fpre=5Fsels, ARRAY=5FSIZE(l=
cdif=5Fpre=5Fsels), CLK=5FSET=5FRATE=5FPARENT);
 	hws[IMX6UL=5FCLK=5FLCDIF=5FSEL]	  =3D imx=5Fclk=5Fhw=5Fmux("lcdif=5Fsel",=
	base + 0x38, 9, 3, lcdif=5Fsels, ARRAY=5FSIZE(lcdif=5Fsels));
+	hws[IMX6UL=5FCLK=5FCSI=5FSEL]		  =3D imx=5Fclk=5Fhw=5Fmux("csi=5Fsel", ba=
se + 0x3c, 9, 2, csi=5Fsels, ARRAY=5FSIZE(csi=5Fsels));
=20
 	hws[IMX6UL=5FCLK=5FLDB=5FDI0=5FDIV=5FSEL]  =3D imx=5Fclk=5Fhw=5Fmux("ldb=
=5Fdi0", base + 0x20, 10, 1, ldb=5Fdi0=5Fdiv=5Fsels, ARRAY=5FSIZE(ldb=5Fdi0=
=5Fdiv=5Fsels));
 	hws[IMX6UL=5FCLK=5FLDB=5FDI1=5FDIV=5FSEL]  =3D imx=5Fclk=5Fhw=5Fmux("ldb=
=5Fdi1", base + 0x20, 11, 1, ldb=5Fdi1=5Fdiv=5Fsels, ARRAY=5FSIZE(ldb=5Fdi1=
=5Fdiv=5Fsels));
--=20
2.25.1