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From:   Stefan Riedmueller <s.riedmueller@phytec.de>
To:     Abel Vesa <abel.vesa@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>
Cc:     Stefan Riedmueller <s.riedmueller@phytec.de>,
        Fabio Estevam <festevam@gmail.com>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        NXP Linux Team <linux-imx@nxp.com>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: [PATCH v2 2/2] clk: imx: imx6ul: Fix csi clk gate register
Date:   Mon, 27 Sep 2021 09:28:57 +0200
Message-Id: <20210927072857.3940880-2-s.riedmueller@phytec.de>
In-Reply-To: <20210927072857.3940880-1-s.riedmueller@phytec.de>
References: <20210927072857.3940880-1-s.riedmueller@phytec.de>
MIME-Version: 1.0
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Precedence: bulk

According to the imx6ul Reference Manual the csi clk gate register is
CCM=5FCCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM=5FCCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.

Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM=5FCCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Tested-by: Fabio Estevam <festevam@gmail.com>
---
Changes in v2:
 - Added comment about ref manual mismatch
 - Added Tested-by from Fabio
---
 drivers/clk/imx/clk-imx6ul.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 206e4c43f68f..520b100bff4b 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -380,7 +380,6 @@ static void =5F=5Finit imx6ul=5Fclocks=5Finit(struct de=
vice=5Fnode *ccm=5Fnode)
 		hws[IMX6ULL=5FCLK=5FESAI=5FIPG]	=3D imx=5Fclk=5Fhw=5Fgate2=5Fshared("esa=
i=5Fipg",	"ahb",		base + 0x70,	0, &share=5Fcount=5Fesai);
 		hws[IMX6ULL=5FCLK=5FESAI=5FMEM]	=3D imx=5Fclk=5Fhw=5Fgate2=5Fshared("esa=
i=5Fmem",	"ahb",		base + 0x70,	0, &share=5Fcount=5Fesai);
 	}
-	hws[IMX6UL=5FCLK=5FCSI]		=3D imx=5Fclk=5Fhw=5Fgate2("csi",		"csi=5Fpodf",=
		base + 0x70,	2);
 	hws[IMX6UL=5FCLK=5FI2C1]		=3D imx=5Fclk=5Fhw=5Fgate2("i2c1",		"perclk",	b=
ase + 0x70,	6);
 	hws[IMX6UL=5FCLK=5FI2C2]		=3D imx=5Fclk=5Fhw=5Fgate2("i2c2",		"perclk",	b=
ase + 0x70,	8);
 	hws[IMX6UL=5FCLK=5FI2C3]		=3D imx=5Fclk=5Fhw=5Fgate2("i2c3",		"perclk",	b=
ase + 0x70,	10);
@@ -391,6 +390,12 @@ static void =5F=5Finit imx6ul=5Fclocks=5Finit(struct d=
evice=5Fnode *ccm=5Fnode)
 	hws[IMX6UL=5FCLK=5FPXP]		=3D imx=5Fclk=5Fhw=5Fgate2("pxp",		"axi",		base =
+ 0x70,	30);
=20
 	/* CCGR3 */
+	/*
+	 * Although the imx6ull reference manual lists CCGR2 as the csi clk
+	 * gate register, tests have shown that it is actually the CCGR3
+	 * register bit 0/1, same as for the imx6ul.
+	 */
+	hws[IMX6UL=5FCLK=5FCSI]		=3D imx=5Fclk=5Fhw=5Fgate2("csi",	"csi=5Fpodf",	=
base + 0x74,	0);
 	hws[IMX6UL=5FCLK=5FUART5=5FIPG]	=3D imx=5Fclk=5Fhw=5Fgate2("uart5=5Fipg",=
	"ipg",		base + 0x74,	2);
 	hws[IMX6UL=5FCLK=5FUART5=5FSERIAL]	=3D imx=5Fclk=5Fhw=5Fgate2("uart5=5Fse=
rial",	"uart=5Fpodf",	base + 0x74,	2);
 	if (clk=5Fon=5Fimx6ul()) {
--=20
2.25.1