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[23.128.96.18]) by mx.google.com with ESMTP id z3si1817156ede.156.2021.09.27.01.34.19; Mon, 27 Sep 2021 01:34:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233539AbhI0Ie2 (ORCPT + 99 others); Mon, 27 Sep 2021 04:34:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233542AbhI0Ie2 (ORCPT ); Mon, 27 Sep 2021 04:34:28 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80192C061740 for ; Mon, 27 Sep 2021 01:32:50 -0700 (PDT) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mUm40-00050w-Hi; Mon, 27 Sep 2021 10:32:40 +0200 Message-ID: Subject: Re: [PATCH v2 2/4] dt-bindings: phy: add imx8 pcie phy driver support From: Lucas Stach To: Richard Zhu , kishon@ti.com, vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, linux-imx@nxp.com Date: Mon, 27 Sep 2021 10:32:39 +0200 In-Reply-To: <1632641983-1455-3-git-send-email-hongxing.zhu@nxp.com> References: <1632641983-1455-1-git-send-email-hongxing.zhu@nxp.com> <1632641983-1455-3-git-send-email-hongxing.zhu@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Sonntag, dem 26.09.2021 um 15:39 +0800 schrieb Richard Zhu: > Add dt-binding for the standalone i.MX8 PCIe PHY driver. > > Signed-off-by: Richard Zhu > --- > .../bindings/phy/fsl,imx8-pcie-phy.yaml | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml > new file mode 100644 > index 000000000000..fd08897fef82 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings > + > +maintainers: > + - Richard Zhu > + > +properties: > + "#phy-cells": > + const: 0 > + > + compatible: > + enum: > + - fsl,imx8mm-pcie-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: PHY module clock > + > + clock-names: > + items: > + - const: phy The clock name should describe what it is used for in the hardware block described by the DT node. So I would think this should be called "ref" or something like this, as I believe this clock is really only used as the reference clock and can be disabled when the refclock is supplied via the pad, right? > + > + fsl,refclk-pad-mode: > + description: | > + Specifies the mode of the refclk pad used. It can be NO_USED(PHY > + refclock is derived from SoC internal source), INPUT(PHY refclock > + is provided externally via the refclk pad) or OUTPUT(PHY refclock > + is derived from SoC internal source and provided on the refclk pad). > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants > + to be used. > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1, 2 ] > + > +required: > + - "#phy-cells" > + - compatible > + - reg > + - clocks > + - clock-names > + - fsl,refclk-pad-mode > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + pcie_phy: pcie-phy@32f00000 { > + compatible = "fsl,imx8mm-pcie-phy"; > + reg = <0x32f00000 0x10000>; > + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; > + clock-names = "phy"; > + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; > + assigned-clock-rates = <100000000>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; > + fsl,refclk-pad-mode = <1>; Include the new header added in patch 1 and use the enum. > + #phy-cells = <0>; > + }; > +...