Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp4113112pxb; Mon, 27 Sep 2021 09:39:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwiiy30cOw3JdYhNrr3cfyKAgd39dlhDYmJLTyQoe7Hz0q36WQCbutfwISHopXdkWvuf+bf X-Received: by 2002:a63:d30e:: with SMTP id b14mr518210pgg.454.1632760753427; Mon, 27 Sep 2021 09:39:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632760753; cv=none; d=google.com; s=arc-20160816; b=OpyuqAPVSH8SUykDVatsJFno9orsTdhBiP02+CDuu1R7uG2ctRl0rW17BwdxCHWAAq r8JcJk4JnQsV0zhsvKxFi/id8iYl32s+p9mcEJWBigv+B+uUdkkdMp4x8IEaOBtxaGm+ fB5t+6ox6xE8jvhESNozAUUDhYCEwerRXHNBUF6dj6Aiq2T20btL7Cif0Iu6pv2Kgt4R Fzajz0o2PC3mHjr28Hb082GpRdwLU7PSVgMQ5xQgme2iX7xaopdNuNGpeoB52A8dTyCS wD7l7Te6UawBvefZZe5XhfzfV4esZyOZMaQXbbu+D+NPwYSXt/J/aamJXQP63g2Bdc0z A/Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=BSzJ9MI1HCyI2LroQSjlIvcFGj03FSNKkHW9ACsfq4A=; b=uXaxt6WQhZFV9eGnzi+mcEAc06RPujTSDHtbn8XAnNHpBgp8+4wbH12WlNlhxvtAPN tRIUzfX3mpmTb2qHACoocVGlEnVS9BlyiaPbYiyUxTh0HBG8EUhUdoaZ3IpipDKQQ8Ep iNlaq06saA818OaukTTVCtrbIk8VH09ankE60pbPrjN96RHExF1UHOrfy9PHZqu7KU0C zti9n9YIr/5pgKFRNLiiW5eA9UWhQSn/dSilSlt4ZzGZBM94SYOU/18dxiqGCk+jeZsM wR2XgflHurgEivZDigsgG3tTCqvxkSt+7zKldVaWxGqy3q9P9gIsMVZA/dT/PN/vzSrI PsWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b="vY/AlZB1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 10si23412323pfl.358.2021.09.27.09.39.00; Mon, 27 Sep 2021 09:39:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b="vY/AlZB1"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235463AbhI0Qjr (ORCPT + 99 others); Mon, 27 Sep 2021 12:39:47 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:34144 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235467AbhI0Qjq (ORCPT ); Mon, 27 Sep 2021 12:39:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=BSzJ9MI1HCyI2LroQSjlIvcFGj03FSNKkHW9ACsfq4A=; b=vY/AlZB163CljHQKnWy4WTj309 NiKmGJaH+/JwqRQMsi09XP6i8ZyBaLtOH/qGayYpAEX0VKugsZtBW6h0hnBpnW0ihTvjDW4t1mxkH rYUuMct2J9IOAETw6vYCqByWYRSit6kuuaNpJPHFFwsUFvk4NY0sSCFNFC7R3hvortmE=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1mUtdk-008T1l-2s; Mon, 27 Sep 2021 18:38:04 +0200 Date: Mon, 27 Sep 2021 18:38:04 +0200 From: Andrew Lunn To: Robert Marko Cc: gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] arm64: dts: marvell: espressobin-ultra: add PHY and switch reset pins Message-ID: References: <20210927154159.2168500-1-robert.marko@sartura.hr> <20210927154159.2168500-3-robert.marko@sartura.hr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210927154159.2168500-3-robert.marko@sartura.hr> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 27, 2021 at 05:41:58PM +0200, Robert Marko wrote: > Both the Topaz switch and 88E1512 PHY have their reset and interrupts > connected to the SoC. > > So, define the Topaz and 88E1512 reset pins in the DTS. > > Defining the interrupt pins wont work as both the 88E1512 and the > Topaz switch uses active LOW IRQ signals but the A37xx GPIO controller > only supports edge triggers. > 88E1512 would require special setup anyway as its INT pin is shared with > the LED2 and you first need to configure it as INT. > > Signed-off-by: Robert Marko Reviewed-by: Andrew Lunn Andrew