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Tue, 28 Sep 2021 09:11:36 +0000 Date: Tue, 28 Sep 2021 12:11:34 +0300 From: Abel Vesa To: Stefan Riedmueller Cc: Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] clk: imx: imx6ul: Move csi_sel mux to correct base register Message-ID: References: <20210927072857.3940880-1-s.riedmueller@phytec.de> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210927072857.3940880-1-s.riedmueller@phytec.de> X-ClientProxiedBy: VI1PR08CA0203.eurprd08.prod.outlook.com (2603:10a6:800:d2::33) To VI1PR0401MB2559.eurprd04.prod.outlook.com (2603:10a6:800:57::8) MIME-Version: 1.0 Received: from ryzen (86.121.85.242) by VI1PR08CA0203.eurprd08.prod.outlook.com (2603:10a6:800:d2::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.13 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?UQSxagk7TDfL/eAkXucdLwYw2WMIGLABAS4Cz2Lpo+BkEjD3OlkYM2x0mxH4?= =?us-ascii?Q?apuBiDevhumTfubR143G/6+FqUvsOsX9FE2IPzShsjuXEepquGIG3oWRFtrt?= =?us-ascii?Q?lInzNSH1oRl+7VHaQy9IyOfHu7kng6x33prMj9e6e/P4sDGZ2Xe6QOugLXR1?= =?us-ascii?Q?wyMjHUnb+PSS2FjeylknyCmtCGuZNLxvWZikYES61nRB3Pyuh4jJrqv5On7n?= =?us-ascii?Q?KVkXdnWnVyywOY4PIVqtd44rOvvZbH+rOgDS1J6lwHpRoUP9OEV+p/xSy+nr?= =?us-ascii?Q?EIt42KLzWu1j3FiUMIaaZS5NpVgyrCgjZC+y9xHcDeqGqgi/obOGDqkf3JnQ?= =?us-ascii?Q?7IFfCDeffrUmjvDohhSgQ66Z7VZYqAG5usa/NrlbXqVmIajQuIHxW7f9oLpx?= =?us-ascii?Q?fxyVJL0PB0rJ0mgWQKOvGU71AfqzLmOLDs5XFHGHUriO4RsEVLI19aGNfOzn?= =?us-ascii?Q?JotPG4cvUf2eSXa+yB9cXww/DewiZK4Nv8roX2+SZyl2+NYLVz1jBiM9/tbL?= =?us-ascii?Q?IX47DEA9EyRvNtlLH2MImkAX0A6ikcc+KhbF4SNFQhDYY5ntxRQgr9HCOQ7J?= =?us-ascii?Q?obp2cYbRfnXCDfhrZBBQ0GBkkUyoVpBHiNhsb4irv+kkmKQTafYMpGRl4Mu2?= =?us-ascii?Q?ls16vbw4WL6gNvNgK/uzn4oT/iWKJnroBD0n9jeAEOdw10E7vMk9IiOnzG5d?= =?us-ascii?Q?fQnKqjyixYvMztEdYy2ThmavwPjIxd3n3AkzD+b4q3mkuAPL3zEs11sEYsPu?= =?us-ascii?Q?fabbLB9kvZML8JTP1VGMDPYiuxudN/ksYWHkuLIH5YQyZsUNfGeyFPFPDry9?= =?us-ascii?Q?oJ2JPdl/0eQOFbpHVCh3Yr85epXJFS+Eq0dZ/ZNpqQ0Iac0rmMFbwu1sWYjf?= =?us-ascii?Q?5PWDsWiQxg0UEWpJ0A9t6lm0juzL9gjcLDScOzMw3P39fQrBuFcpZpyKi3Fy?= =?us-ascii?Q?rGo7E73rFvjZvzUgG/t4Kv8UC8GHSVElFzjDz+RoHh2GFWHOai+3qfeNbgBR?= =?us-ascii?Q?RwXbGn7z4JxLL+UWaCABNd5FmxDaUNpUZY/aHBCR8NkFzOm5pn14Ld8UJew8?= =?us-ascii?Q?InRpF8hShYz+YoxCkrfSqgtDep/I1gBvmnBKszGYDNIJQ1q4bO5o6NzfmK6N?= =?us-ascii?Q?K1bQDIEvwN4SaJVm+kxKrNT0k9/C5TrxRlu5S2fSbZpkQd6h+taHWPWAy7/9?= =?us-ascii?Q?zb+SZoifmU56DwbLYTFF1X5M0hI092xt/hgEP/kZQmkvgH6zrnv8QHvmBmn/?= =?us-ascii?Q?KeslOpKBDxuEmDEzijlzZDT4Cku2Z75YvpT/v4au4wpoNRFrbbT/VKNUyc3u?= =?us-ascii?Q?FKqS0HndIhq4v1E/Ccu+EjQi?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3952a28f-3e07-47e4-001e-08d9825ff913 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0401MB2559.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2021 09:11:36.5650 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OKf2vR4Xe7MbTarHFCkXZnBi6myh7k9c9sWWk3HdFD6/n0BF9XnT68PL0SB1DMJpOke7zbfn3pTpOmKuyCRA+w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6239 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21-09-27 09:28:56, Stefan Riedmueller wrote: > The csi_sel mux register is located in the CCM register base and not the > CCM_ANALOG register base. So move it to the correct position in code. > > Otherwise changing the parent of the csi clock can lead to a complete > system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely > modified. > > Also remove the SET_RATE_PARENT flag since one possible supply for the > csi_sel mux is the system PLL which we don't want to modify. > > Signed-off-by: Stefan Riedmueller Applied both. Thanks. > --- > No changes in v2. > --- > drivers/clk/imx/clk-imx6ul.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c > index 5dbb6a937732..206e4c43f68f 100644 > --- a/drivers/clk/imx/clk-imx6ul.c > +++ b/drivers/clk/imx/clk-imx6ul.c > @@ -161,7 +161,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) > hws[IMX6UL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); > hws[IMX6UL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); > hws[IMX6UL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); > - hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); > > /* Do not bypass PLLs initially */ > clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); > @@ -270,6 +269,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) > hws[IMX6UL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); > hws[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_hw_mux_flags("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT); > hws[IMX6UL_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); > + hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); > > hws[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); > hws[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); > -- > 2.25.1 >