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Subject: Re: [net-next v3 PATCH] octeontx2-pf: Use hardware register for CQE count
From:   patchwork-bot+netdevbpf@kernel.org
Message-Id: <163283520646.29265.11641226830844674997.git-patchwork-notify@kernel.org>
Date:   Tue, 28 Sep 2021 13:20:06 +0000
References: <20210928055526.19286-1-gakula@marvell.com>
In-Reply-To: <20210928055526.19286-1-gakula@marvell.com>
To:     Geetha sowjanya <gakula@marvell.com>
Cc:     netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        kuba@kernel.org, davem@davemloft.net, sgoutham@marvell.com,
        sbhatta@marvell.com, hkelam@marvell.com
Precedence: bulk

Hello:

This patch was applied to netdev/net-next.git (refs/heads/master):

On Tue, 28 Sep 2021 11:25:26 +0530 you wrote:
> Current driver uses software CQ head pointer to poll on CQE
> header in memory to determine if CQE is valid. Software needs
> to make sure, that the reads of the CQE do not get re-ordered
> so much that it ends up with an inconsistent view of the CQE.
> To ensure that DMB barrier after read to first CQE cacheline
> and before reading of the rest of the CQE is needed.
> But having barrier for every CQE read will impact the performance,
> instead use hardware CQ head and tail pointers to find the
> valid number of CQEs.
> 
> [...]

Here is the summary with links:
  - [net-next,v3] octeontx2-pf: Use hardware register for CQE count
    https://git.kernel.org/netdev/net-next/c/af3826db74d1

You are awesome, thank you!
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