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Subject: Re: [PATCH][next] rtc: msc313: Fix unintentional sign extension issue
 on left shift of a u16
To:     Daniel Palmer <daniel@0x0f.com>
Cc:     Daniel Palmer <daniel@thingy.jp>,
        Romain Perier <romain.perier@gmail.com>,
        Alessandro Zummo <a.zummo@towertech.it>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Nobuhiro Iwamatsu <iwamatsu@nigauri.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-rtc@vger.kernel.org, kernel-janitors@vger.kernel.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
References: <20210928123906.988813-1-colin.king@canonical.com>
 <CAFr9PXnMXPmuaUnfr-VwaZDX1hY8ZDtp1+UxOau6DKpUP9FdzQ@mail.gmail.com>
From:   Colin Ian King <colin.king@canonical.com>
Message-ID: <8f21ec82-201d-efee-d1db-382a7885d38f@canonical.com>
Date:   Tue, 28 Sep 2021 14:34:49 +0100
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On 28/09/2021 14:31, Daniel Palmer wrote:
> Hi Colin,
> 
> On Tue, 28 Sept 2021 at 21:39, Colin King <colin.king@canonical.com> wrote:
>> Shifting the u16 value returned by readw by 16 bits to the left
>> will be promoted to a 32 bit signed int and then sign-extended
>> to an unsigned long. If the top bit of the readw is set then
>> the shifted value will be sign extended and the top 32 bits of
>> the result will be set.
> 
> Ah,.. C is fun in all the wrong places. :)
> These chips are full of 32bit registers that are split into two 16
> registers 4 bytes apart when seen from the ARM CPU so we probably have
> this same mistake in a few other places.
> 
> A similar pattern is used a bit later on in the same file to read the counter:
> 
> seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L)
> | (readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16);

Ah, I missed that one! I'll send a V2.

> 
> I guess it works at the moment because the top bit won't be set until 2038.

I hope to be retired by then, but I guess fixing it up before 2038 is a
good idea ;-)

> 
> Thanks,
> 
> Daniel
>