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Wed, 29 Sep 2021 10:44:01 +0000 From: "Liu, Yi L" To: Jean-Philippe Brucker CC: "alex.williamson@redhat.com" , "jgg@nvidia.com" , "hch@lst.de" , "jasowang@redhat.com" , "joro@8bytes.org" , "Tian, Kevin" , "parav@mellanox.com" , "lkml@metux.net" , "pbonzini@redhat.com" , "lushenming@huawei.com" , "eric.auger@redhat.com" , "corbet@lwn.net" , "Raj, Ashok" , "yi.l.liu@linux.intel.com" , "Tian, Jun J" , "Wu, Hao" , "Jiang, Dave" , "jacob.jun.pan@linux.intel.com" , "kwankhede@nvidia.com" , "robin.murphy@arm.com" , "kvm@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "dwmw2@infradead.org" , "linux-kernel@vger.kernel.org" , "baolu.lu@linux.intel.com" , "david@gibson.dropbear.id.au" , "nicolinc@nvidia.com" Subject: RE: [RFC 17/20] iommu/iommufd: Report iova range to userspace Thread-Topic: [RFC 17/20] iommu/iommufd: Report iova range to userspace Thread-Index: AQHXrSGpfnufovxqLESc6zzFg8xwc6uwJ7eAgAq5dCA= Date: Wed, 29 Sep 2021 10:44:01 +0000 Message-ID: References: <20210919063848.1476776-1-yi.l.liu@intel.com> <20210919063848.1476776-18-yi.l.liu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows authentication-results: linaro.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5658.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9caa162b-cd3f-4a13-f477-08d983360c9e X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2021 10:44:01.1627 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Rk5sMINXhu78CeUfhVTm5uaH0tGR3yugiW0fypKpw/GXlbAcMUtyrzeBP2c1+BOlHaTU2e7XNKa/XVQIONIe7A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5643 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jean-Philippe Brucker > Sent: Wednesday, September 22, 2021 10:49 PM >=20 > On Sun, Sep 19, 2021 at 02:38:45PM +0800, Liu Yi L wrote: > > [HACK. will fix in v2] > > > > IOVA range is critical info for userspace to manage DMA for an I/O addr= ess > > space. This patch reports the valid iova range info of a given device. > > > > Due to aforementioned hack, this info comes from the hacked vfio type1 > > driver. To follow the same format in vfio, we also introduce a cap chai= n > > format in IOMMU_DEVICE_GET_INFO to carry the iova range info. > [...] > > diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h > > index 49731be71213..f408ad3c8ade 100644 > > --- a/include/uapi/linux/iommu.h > > +++ b/include/uapi/linux/iommu.h > > @@ -68,6 +68,7 @@ > > * +---------------+------------+ > > * ... > > * @addr_width: the address width of supported I/O address spaces. > > + * @cap_offset: Offset within info struct of first cap > > * > > * Availability: after device is bound to iommufd > > */ > > @@ -77,9 +78,11 @@ struct iommu_device_info { > > #define IOMMU_DEVICE_INFO_ENFORCE_SNOOP (1 << 0) /* IOMMU > enforced snoop */ > > #define IOMMU_DEVICE_INFO_PGSIZES (1 << 1) /* supported page > sizes */ > > #define IOMMU_DEVICE_INFO_ADDR_WIDTH (1 << 2) /* > addr_wdith field valid */ > > +#define IOMMU_DEVICE_INFO_CAPS (1 << 3) /* info > supports cap chain */ > > __u64 dev_cookie; > > __u64 pgsize_bitmap; > > __u32 addr_width; > > + __u32 cap_offset; >=20 > We can also add vendor-specific page table and PASID table properties as > capabilities, otherwise we'll need giant unions in the iommu_device_info > struct. That made me wonder whether pgsize and addr_width should also > be > separate capabilities for consistency, but this way might be good enough. > There won't be many more generic capabilities. I have "output address > width" what do you mean by "output address width"? Is it the output address of stage-1 translation? > and "PASID width", the rest is specific to Arm and SMMU table > formats. When coming to nested translation support, the stage-1 related info are likely to be vendor-specific, and will be reported in cap chain. Regards, Yi Liu > Thanks, > Jean >=20 > > }; > > > > #define IOMMU_DEVICE_GET_INFO _IO(IOMMU_TYPE, IOMMU_BASE + > 1) > > -- > > 2.25.1 > >