Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp956686pxb; Wed, 29 Sep 2021 13:27:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKj6aofdSp3HTtDZPg2YexEQty2bMVO6VEa9BQybpshO+crNMubZW9qskzPAmu7a9ppMZ/ X-Received: by 2002:a17:902:7845:b0:13d:9664:91e3 with SMTP id e5-20020a170902784500b0013d966491e3mr389193pln.13.1632947231310; Wed, 29 Sep 2021 13:27:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632947231; cv=none; d=google.com; s=arc-20160816; b=oo2NhyjGx7a0yyFACZJMCW/u3yzGXwHxM4MoqoFaqXd6OTLsnS5gytQ+EuIR/WmGz3 fkxem2dj7cNYGHkFozIs1WIXdqiIbcKDvsYVfbgSUITuF0cTKOOJLlNNpJe7sCZhXxxo gL0L78tC0knN/WJjYcPPMB4CyeEGyP+OrQYjUYe/8J643HtZQEt5Z+J44eS7inNILuYv y2YPQfKIIyDDvVNZgnkBYlLxiRSQdV01jmFiBisAUtuJkM+HFI+hguYDMNxM40gdQ0mC LOv3mEl2z3HTAsowWFx0LuUdVAjQV84wrjjAaZXtA0+ELPEgedG2EwUfM2jyhOFk9DIX iU3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=Lh+F5ZjCx0bOA0ZJvvdGRxDGTO4CVU+5ejZ1orJFARo=; b=MqziBSwvyGQ6InjayudzzhZUOV9xBSMGLPWTPTRcuGb8rzJZwJqVnPyud29LGxHauO Ytrw2Okrvowf4cZMaKmgxI5ZKa3+S+MFI3TC4ly3msfTDKOUI6dQ5UzL9KMe1ZFyBrbv 9XAnhB2ZWX4DeKCLsjtPxjlKFkVgS22TFDoLOgvWlsL51xehrsS8kacbC/fnG6DGyHCO YOG4HuVFwRNZ+++s5Tpu7/IsQBUJuRn26OWi5NVlNQV0en6KAXsfF7vkMusn6DkeCUFj cBz8F1q2IwsB+Nqk/PBK2GHELRFhBwQHHXLoCI14/Q1GCsEdXZU04Ub2GQC7WMiy8DEC G8qQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=MUWnnwDT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n5si2556386pjv.101.2021.09.29.13.26.58; Wed, 29 Sep 2021 13:27:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=MUWnnwDT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346693AbhI2U0e (ORCPT + 99 others); Wed, 29 Sep 2021 16:26:34 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:39554 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346361AbhI2U0d (ORCPT ); Wed, 29 Sep 2021 16:26:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=Lh+F5ZjCx0bOA0ZJvvdGRxDGTO4CVU+5ejZ1orJFARo=; b=MUWnnwDTA13YTmHBToqcVGDNT5 ePCd5dqFdM8DbuueNSvx9nvtXef2xRllw5xAQodxwVgSP22IWwn95jfAu9MY5mjXm9tczXEM+7wi5 fLdgN9nLR2ly4pwjSQgu4+siBw1mWaxFZfmDlbTr8cBJQkGWuVNAcjPhvYO8ya8Hc7oQ=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1mVg8E-008qF0-Kf; Wed, 29 Sep 2021 22:24:46 +0200 Date: Wed, 29 Sep 2021 22:24:46 +0200 From: Andrew Lunn To: Asmaa Mnebhi Cc: Linus Walleij , Andy Shevchenko , "open list:GPIO SUBSYSTEM" , netdev , linux-kernel , ACPI Devel Maling List , Jakub Kicinski , Bartosz Golaszewski , "David S. Miller" , "Rafael J. Wysocki" , David Thompson Subject: Re: [PATCH v3 1/2] gpio: mlxbf2: Introduce IRQ support Message-ID: References: <20210923202216.16091-1-asmaa@nvidia.com> <20210923202216.16091-2-asmaa@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > In KSZ9031, Register MII_KSZPHY_INTCS=0x1B reports all interrupt events and > clear on read. So if there are 4 different interrupts, once it is read once, all 4 clear at once. > The micrel.c driver has defined ack_interrupt to read the above reg and is called every time the > interrupt handler phy_interrupt is called. So in this case, we should be good. > The code flow in our case would look like this: > - 2 interrupt sources (for example, link down followed by link up) set in MII_KSZPHY_INTCS > - interrupt handler (phy_interrupt) reads MII_KSZPHY_INT which automatically clears both > interrupts > - another internal source triggers and sets the register. > - The second edge will be caught accordingly by the GPIO. I still think there is a small race window. You product manager needs to decide if that is acceptable, or if you should poll the PHY. Anyway, it is clear the hardware only does level interrupts, so the GPIO driver should only accept level interrupts. -EINVAL otherwise. I also assume you have a ACPI blob which indicates what sort of interrupts that should be used, level low, falling edge etc. Since that is outside of the kernel, i will never know what you decide to put there. Ideally, until the hardware is fixed, you should not list any interrupt and fallback to polling. Andrew