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Message-ID: <3078b365b5ddfad198a5c8a097f2e7edb9730e2c.camel@gmail.com>
Subject: Re: [PATCH v1 2/2] mmc: sdhci: Use the SW timer when the HW timer
 cannot meet the timeout value required by the device
From:   Bean Huo <huobean@gmail.com>
To:     Adrian Hunter <adrian.hunter@intel.com>,
        Ulf Hansson <ulf.hansson@linaro.org>
Cc:     Bean Huo <beanhuo@micron.com>, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org
Date:   Thu, 30 Sep 2021 10:34:38 +0200
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Hi Adrian,


Thanks.
I want to give a short conclusion  for our discussion:

Based on your information, these sounds disable of HW timer timeout
interrupt will make eMMC host controller malfunction, in another word,
the disable of timeout interrupt will make the eMMC host cannot
correctly provide the completion interrupt. And unless only when the
SOC vendor signals that their SOC supports that the host side SW can
disable this HW timeout interrupt, as TI does.

I studied the SDHCI Spec, and tried to see if there is this kind of
support statement, but not been found yet. I will check with other SOC
vendors.

I have one more question, if you know, please give me your information.

I did testing on HW timer bahevior in case CQE is on.  Currently, we
always set the HW timer with the maximum timeout value if CQE is on.
Based on my testing, the HW timer will never timeout when we enable
CQE. I changed the HW timer value to be lower, it is the same result.
Do you know that the HW timer will be inactivated in case CQE is
on?  but its timeout interrupt is still enabled.

Kind regards,
Bean