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From:   "Winkler, Tomas" <tomas.winkler@intel.com>
To:     Mauro Carvalho Chehab <mchehab+huawei@kernel.org>,
        Linux Doc Mailing List <linux-doc@vger.kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC:     Jonathan Corbet <corbet@lwn.net>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        "Box, David E" <david.e.box@intel.com>,
        Hans de Goede <hdegoede@redhat.com>,
        Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>,
        "Mashiah, Tamar" <tamar.mashiah@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "platform-driver-x86@vger.kernel.org" 
        <platform-driver-x86@vger.kernel.org>
Subject: RE: [PATCH 7/7] ABI: sysfs-platform-intel-pmc: add blank lines to
 make it valid for ReST
Thread-Topic: [PATCH 7/7] ABI: sysfs-platform-intel-pmc: add blank lines to
 make it valid for ReST
Thread-Index: AQHXs5BhWDSB44ICBEuOmGxnwUE14Ku8RYTw
Date:   Thu, 30 Sep 2021 08:37:12 +0000
Message-ID: <b21707f01a3646bf929db9c9df3653d7@intel.com>
References: <cover.1632740376.git.mchehab+huawei@kernel.org>
 <3673e1a255ad4100c933af215b60d68ba126f820.1632740376.git.mchehab+huawei@kernel.org>
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> 
> The ReST format requires blank lines before/after identation changes, for it
> to properly detect lists.
> 
> Fixes: ee7abc105e2b ("platform/x86: intel_pmc_core: export platform global
> reset bits via etr3 sysfs file")
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Ack.
> ---
> 
> See [PATCH 0/7] at:
> https://lore.kernel.org/all/cover.1632740376.git.mchehab+huawei@kernel.o
> rg/T/#t
> 
>  Documentation/ABI/testing/sysfs-platform-intel-pmc | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-platform-intel-pmc
> b/Documentation/ABI/testing/sysfs-platform-intel-pmc
> index ef199af75ab0..f31d59b21f9b 100644
> --- a/Documentation/ABI/testing/sysfs-platform-intel-pmc
> +++ b/Documentation/ABI/testing/sysfs-platform-intel-pmc
> @@ -11,8 +11,10 @@ Description:
>  		to take effect.
> 
>  		Display global reset setting bits for PMC.
> +
>  			* bit 31 - global reset is locked
>  			* bit 20 - global reset is set
> +
>  		Writing bit 20 value to the etr3 will induce
>  		a platform "global reset" upon consequent platform reset,
>  		in case the register is not locked.
> --
> 2.31.1