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Thu, 30 Sep 2021 08:49:03 +0000 From: "Tian, Kevin" To: Jason Gunthorpe , "Lu, Baolu" CC: Jean-Philippe Brucker , Alex Williamson , "Liu, Yi L" , "hch@lst.de" , "jasowang@redhat.com" , "joro@8bytes.org" , "parav@mellanox.com" , "lkml@metux.net" , "pbonzini@redhat.com" , "lushenming@huawei.com" , "eric.auger@redhat.com" , "corbet@lwn.net" , "Raj, Ashok" , "yi.l.liu@linux.intel.com" , "Tian, Jun J" , "Wu, Hao" , "Jiang, Dave" , "jacob.jun.pan@linux.intel.com" , "kwankhede@nvidia.com" , "robin.murphy@arm.com" , "kvm@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "dwmw2@infradead.org" , "linux-kernel@vger.kernel.org" , "baolu.lu@linux.intel.com" , "david@gibson.dropbear.id.au" , "nicolinc@nvidia.com" Subject: RE: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO Thread-Topic: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO Thread-Index: AQHXrSGNbNtRgavabUSKJjvt8l12BauwlhaAgAAouwCAACufAIAAgyUAgAAUFACAAAdkgIAAB/8AgArAWrA= Date: Thu, 30 Sep 2021 08:49:03 +0000 Message-ID: References: <20210919063848.1476776-1-yi.l.liu@intel.com> <20210919063848.1476776-11-yi.l.liu@intel.com> <20210922152407.1bfa6ff7.alex.williamson@redhat.com> <20210922234954.GB964074@nvidia.com> <20210923112716.GE964074@nvidia.com> <20210923122220.GL964074@nvidia.com> In-Reply-To: <20210923122220.GL964074@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5433.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a9ee9a22-cfb1-43c2-2d72-08d983ef27b8 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2021 08:49:03.5255 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vjS2p4SHKj55HAS3qBrcTF1uj5Snc7NLwN8lpLyROR3Ak4cu5Rn65H1JdJS95Udhgk8P2ufIs1F5BtUvj4Y3Dg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR11MB3764 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jason Gunthorpe > Sent: Thursday, September 23, 2021 8:22 PM >=20 > > > These are different things and need different bits. Since the ARM pat= h > > > has a lot more code supporting it, I'd suggest Intel should change > > > their code to use IOMMU_BLOCK_NO_SNOOP and abandon > IOMMU_CACHE. > > > > I didn't fully get this point. The end result is same, i.e. making the = DMA > > cache-coherent when IOMMU_CACHE is set. Or if you help define the > > behavior of IOMMU_CACHE, what will you define now? >=20 > It is clearly specifying how the kernel API works: >=20 > !IOMMU_CACHE > must call arch cache flushers > IOMMU_CACHE - > do not call arch cache flushers > IOMMU_CACHE|IOMMU_BLOCK_NO_SNOOP - > dot not arch cache flushers, and ignore the no snoop bit. Who will set IOMMU_BLOCK_NO_SNOOP? I feel this is arch specific knowledge about how cache coherency is implemented, i.e.=20 when IOMMU_CACHE is set intel-iommu driver just maps it to blocking no-snoop. It's not necessarily to be an attribute in=20 the same level as IOMMU_CACHE? >=20 > On Intel it should refuse to create a !IOMMU_CACHE since the HW can't > do that.=20 Agree. In reality I guess this is not hit because all devices are marked coherent on Intel platforms... Baolu, any insight here? Thanks Kevin