Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Thu, 30 Sep 2021 19:08:22 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Tian, Kevin" <kevin.tian@intel.com>
Cc:     "Lu, Baolu" <baolu.lu@intel.com>,
        Jean-Philippe Brucker <jean-philippe@linaro.org>,
        Alex Williamson <alex.williamson@redhat.com>,
        "Liu, Yi L" <yi.l.liu@intel.com>, "hch@lst.de" <hch@lst.de>,
        "jasowang@redhat.com" <jasowang@redhat.com>,
        "joro@8bytes.org" <joro@8bytes.org>,
        "parav@mellanox.com" <parav@mellanox.com>,
        "lkml@metux.net" <lkml@metux.net>,
        "pbonzini@redhat.com" <pbonzini@redhat.com>,
        "lushenming@huawei.com" <lushenming@huawei.com>,
        "eric.auger@redhat.com" <eric.auger@redhat.com>,
        "corbet@lwn.net" <corbet@lwn.net>,
        "Raj, Ashok" <ashok.raj@intel.com>,
        "yi.l.liu@linux.intel.com" <yi.l.liu@linux.intel.com>,
        "Tian, Jun J" <jun.j.tian@intel.com>, "Wu, Hao" <hao.wu@intel.com>,
        "Jiang, Dave" <dave.jiang@intel.com>,
        "jacob.jun.pan@linux.intel.com" <jacob.jun.pan@linux.intel.com>,
        "kwankhede@nvidia.com" <kwankhede@nvidia.com>,
        "robin.murphy@arm.com" <robin.murphy@arm.com>,
        "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>,
        "dwmw2@infradead.org" <dwmw2@infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "baolu.lu@linux.intel.com" <baolu.lu@linux.intel.com>,
        "david@gibson.dropbear.id.au" <david@gibson.dropbear.id.au>,
        "nicolinc@nvidia.com" <nicolinc@nvidia.com>
Subject: Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO
Message-ID: <20210930220822.GG964074@nvidia.com>
References: <20210919063848.1476776-1-yi.l.liu@intel.com>
 <20210919063848.1476776-11-yi.l.liu@intel.com>
 <20210922152407.1bfa6ff7.alex.williamson@redhat.com>
 <20210922234954.GB964074@nvidia.com>
 <BN9PR11MB543333AD3C81312115686AAA8CA39@BN9PR11MB5433.namprd11.prod.outlook.com>
 <YUxTvCt1mYDntO8z@myrica>
 <20210923112716.GE964074@nvidia.com>
 <BN9PR11MB5433BCFCF3B0CB657E9BFE898CA39@BN9PR11MB5433.namprd11.prod.outlook.com>
 <20210923122220.GL964074@nvidia.com>
 <BN9PR11MB5433F33CB7CFBCD41BE2F5C68CAA9@BN9PR11MB5433.namprd11.prod.outlook.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <BN9PR11MB5433F33CB7CFBCD41BE2F5C68CAA9@BN9PR11MB5433.namprd11.prod.outlook.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?huhA6NyoZNr1q5faQSouxgjumTqP4iWRUWNlQ6Ac/wuP71ZBZEdVDQgf1hlJ?=
 =?us-ascii?Q?Qpbz+ZjxYhxWgCcbMS5yj2C1ru/yT0owT6Ll2A3//heLpKyrLqKQMkjtFWN8?=
 =?us-ascii?Q?+aw7TjdM3do+BGKg8vHuEi5GGUe/8A6+joozfcrO7rPZNdhEE3r9pf15CZ4W?=
 =?us-ascii?Q?Z52Zl7h1jPJnGDVjU/TwU90lC/Au1t+Ab3dHN6e2a+gn+2s+vuocieRQcQQ4?=
 =?us-ascii?Q?4wuz2lklUA4oE6xlO/OLmrDvTRCWhK9W8U9Dp55VXgEQLzk1ead89B4d7NX7?=
 =?us-ascii?Q?ggi6PjZ0+QCiGD6GBBRkCyt3dMoPULj/Eqq9VYEAfJwWOE3h2BR3fRCoHbfG?=
 =?us-ascii?Q?fW1ZcxLfM9JcaCZfAyukMA9Wqyurmx2qFF7JKjV/2bMmg+JVP4qg+afaQDhQ?=
 =?us-ascii?Q?r16bNXVrqndW8O6tFLH2GqBCBffdL+dxJbPyxl42woNcRMXv1eTb5zIRY3pP?=
 =?us-ascii?Q?fi64aXBEVobI6ad6Wtsw2jFG3Oba2WQoRUJE9+tBc7oY4iYY5wO0M4B3MYBF?=
 =?us-ascii?Q?1AXveexOdcn983bMtWo154L0sZQjb7zK2WBH614JX10KawP7WLI/hIvOCdfI?=
 =?us-ascii?Q?zt6zsLxCKvw+B4TD3x4P8Cs6sIxADR2144ynsOiKbtuzk7OfsloZloZbGbcs?=
 =?us-ascii?Q?xZIBXUAz2GobRK6dnXea/En63xpWmXasSl4cYN7xoLl9eMNR6+qZ5sPDJinr?=
 =?us-ascii?Q?7fU0/EsUTDqOJXlbWCn8UfHfcuDjw31B6ttZ8S6Jwkman48JtPA1w/4b8rPC?=
 =?us-ascii?Q?5uex8zfSBg4KFErXdtnrRyX1gmdtvHDJPS4IDYm4k4YKEPaoXqfGaxo80Klv?=
 =?us-ascii?Q?buifk2o4Ray7JMu4Wn5I6CipJkNZnaR3KEACnUD0LoCauURxd5IdSinsi5QR?=
 =?us-ascii?Q?8QjSMWHvdvgZULtTrKegKenNVw1+MVnOZxeUmb8vdyDePS1XPiP6W8XExUm2?=
 =?us-ascii?Q?CYQe9mVSziuUWhhEzab96C22SPW7DoRcwFP0tqeIwtzRCtMGC2NGf2YdgVGe?=
 =?us-ascii?Q?WNsJ//GdY0aThhzJyOEJFemSUj+BEyYrNREAA2WskwnPY8wUdXBl+2kWuhw1?=
 =?us-ascii?Q?E8e5Dg4co8iS/0Bn5XBO1SBCv/dhCnpoed8hcBDSlWwJY4XbWSGZOFiXCShe?=
 =?us-ascii?Q?c/cCAcjPYnA1Nt5PLqaUMJQbpdtOsxecH8Mw4bqIzDJsx47uPJDDdqt8CQj6?=
 =?us-ascii?Q?LbA4VAhkZVMMPS0IhskgqvUgqWj2bjKVqxFzcQulzSG4SEDU/jhHMhnP/bua?=
 =?us-ascii?Q?jSDUB7/adR9ECrQIfITcf7fK20RUjgs9qM5a+K9stcinQd3WZS/zFfuHpFZ7?=
 =?us-ascii?Q?g5hHK0fwqv/qscgSchpqQfuf?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 0bbac8bb-0a19-476f-8973-08d9845ed251
X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB5506.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 22:08:24.3412
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: zmZu0OkRqtyfRiuAKUaTtb37dctGIm9NFs8l4DeDOt1r+910l9lmmTkGK8M1T9ap
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5223
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Thu, Sep 30, 2021 at 08:49:03AM +0000, Tian, Kevin wrote:
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > Sent: Thursday, September 23, 2021 8:22 PM
> > 
> > > > These are different things and need different bits. Since the ARM path
> > > > has a lot more code supporting it, I'd suggest Intel should change
> > > > their code to use IOMMU_BLOCK_NO_SNOOP and abandon
> > IOMMU_CACHE.
> > >
> > > I didn't fully get this point. The end result is same, i.e. making the DMA
> > > cache-coherent when IOMMU_CACHE is set. Or if you help define the
> > > behavior of IOMMU_CACHE, what will you define now?
> > 
> > It is clearly specifying how the kernel API works:
> > 
> >  !IOMMU_CACHE
> >    must call arch cache flushers
> >  IOMMU_CACHE -
> >    do not call arch cache flushers
> >  IOMMU_CACHE|IOMMU_BLOCK_NO_SNOOP -
> >    dot not arch cache flushers, and ignore the no snoop bit.
> 
> Who will set IOMMU_BLOCK_NO_SNOOP?

Basically only qemu due to specialized x86 hypervisor knowledge.

The only purpose of this attribute is to support a specific
virtualization use case where a whole bunch of stuff is broken
together:
 - the cache maintenance instructions are not available to a guest
 - the guest isn't aware that the instructions don't work and tells
   the device to issue no-snoop TLPs
 - The device ignores the 'disable no-snoop' flag in the PCIe config
   space

Thus things become broken.

Jason