Received: by 2002:a05:6a10:d5a5:0:0:0:0 with SMTP id gn37csp932855pxb; Thu, 30 Sep 2021 22:37:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyF0tMEcI5UK1pnyzwj1dW0R1nnvLRhn0SuO57as9X/CCuC9IRHWRGvyV3I+bawjBFxSrmA X-Received: by 2002:a17:906:544f:: with SMTP id d15mr4117082ejp.520.1633066643686; Thu, 30 Sep 2021 22:37:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633066643; cv=none; d=google.com; s=arc-20160816; b=0BCrQ/BP6Z9CV84BuGEUJP9FKIUr599BnWyCzpHgWKWLxm8tppu4o6bML6L23jNGHX 6LtZrJC/W134Yb3AyYUJQlZrwyhxEL8vxppw+2npBpT+VN+Jd7eh50kEH0j1kzVVQe/V tXu49AhKeOhALiNnrrbIZuxv1H9bF0Qr2IkSrRM3PDiY9TLTofs4LLjJUbEzgE95A/FA /vIkpwIr3CSleXSUiQI+bDaNllAa5amRvfnD0CiuJg+57qOwe6IrlbJtp1o3PqmiY34X NGw0pUJiPs+TGQSMu2GW1PI0yu0J14my7rUwF1RV7STUjK7XzIqEYA31GjDfwXehfqKj oZwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject:dmarc-filter:sender:dkim-signature; bh=Dg9UyJAGvh1utQRxDwx+mgOUXPzyBeM2J8AXutvknM0=; b=lfBIIJSydrmOb8lukfrBYpqHJoJFYVtk/oGxe+fR5nv3m2S5oRvrU1mGh6zn3kO56s pduP5tdq3Oq+KY5xvMp4po38UxYmPKa3nvTNNd5KG2K2JuYcjIRfXZ+c0pyq4qzCi64t zV95Njh7C4IuBBefREI7qihjbFES8rLu6JXao62uMTkoDtc3yCDioaoKEElpCdkM6CTB 5WUsDn2VdO5gQbGErdWkz2/lyLOSi2BYGjq3t2Pxpd/9OIGI/QDr/daCBy6ZOvwEoRrU 33AAwpa4OVltlqJayp0yF77c0WJCJ0mJWRv9p8SAVEi3bujduzv9wSrY6u2uie2WcCMy tWcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=QngNJ9l6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x16si10222633edd.121.2021.09.30.22.36.58; Thu, 30 Sep 2021 22:37:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=QngNJ9l6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241541AbhJAFgU (ORCPT + 99 others); Fri, 1 Oct 2021 01:36:20 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:60458 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351909AbhJAFgT (ORCPT ); Fri, 1 Oct 2021 01:36:19 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1633066475; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=Dg9UyJAGvh1utQRxDwx+mgOUXPzyBeM2J8AXutvknM0=; b=QngNJ9l69IfLMI4jPa8nQMltCOLN3EmgOK8s6KuTFdfnH/Kj6imjVRlkL6Llvpe9/izqv1l8 R5h6QZVfT2ebezYNZBUxJ7/jeqclYuYJsyd5c6LJcg8EjarwUvVIX6shmrI8IMOGPghrTS6C 5UXkmxqZ4I+8TLBCbF5+0wQPXmo= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-east-1.postgun.com with SMTP id 61569deb713d5d6f96e7aa5f (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 01 Oct 2021 05:34:35 GMT Sender: rnayak=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 82BABC4360C; Fri, 1 Oct 2021 05:34:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=2.0 tests=ALL_TRUSTED,BAYES_00, NICE_REPLY_A,SPF_FAIL,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from [192.168.1.100] (unknown [49.207.222.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3F83CC4338F; Fri, 1 Oct 2021 05:34:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.codeaurora.org 3F83CC4338F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=codeaurora.org Subject: Re: [PATCH] pinctrl: qcom: Add egpio feature support To: Bjorn Andersson Cc: agross@kernel.org, linus.walleij@linaro.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Sodagudi References: <1631860648-31774-1-git-send-email-rnayak@codeaurora.org> <2d2891e2-0cdf-1938-f9a1-77135066f5de@codeaurora.org> From: Rajendra Nayak Message-ID: Date: Fri, 1 Oct 2021 11:04:28 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/30/2021 8:25 PM, Bjorn Andersson wrote: > On Thu 30 Sep 02:46 PDT 2021, Rajendra Nayak wrote: > >> >> >> On 9/21/2021 9:56 PM, Bjorn Andersson wrote: >>> On Tue 21 Sep 03:39 PDT 2021, Rajendra Nayak wrote: >>> >>>> >>>> >>>> On 9/20/2021 6:14 AM, Bjorn Andersson wrote: >>>>> On Fri 17 Sep 01:37 CDT 2021, Rajendra Nayak wrote: >>>>> >>>>>> From: Prasad Sodagudi >>>>>> >>>>>> egpio is a scheme which allows special power Island Domain IOs >>>>>> (LPASS,SSC) to be reused as regular chip GPIOs by muxing regular >>>>>> TLMM functions with Island Domain functions. >>>>>> With this scheme, an IO can be controlled both by the cpu running >>>>>> linux and the Island processor. This provides great flexibility to >>>>>> re-purpose the Island IOs for regular TLMM usecases. >>>>>> >>>>>> 2 new bits are added to ctl_reg, egpio_present is a read only bit >>>>>> which shows if egpio feature is available or not on a given gpio. >>>>>> egpio_enable is the read/write bit and only effective if egpio_present >>>>>> is 1. Once its set, the Island IO is controlled from Chip TLMM. >>>>>> egpio_enable when set to 0 means the GPIO is used as Island Domain IO. >>>>>> >>>>>> The support exists on most recent qcom SoCs, and we add support >>>>>> for sm8150/sm8250/sm8350 and sc7280 as part of this patch. >>>>>> >>>>> >>>>> I was under the impression that this feature would allow you to >>>>> repurpose pins for use either by the remote island or by apps. >>>> >>>> thats right, you can repurpose the pins for usage by apps by setting >>>> the egpio_enable to 1, when set to 0 its owned by the island processor. >>> >>> Good. >>> >>>>> >>>>> But if I understand your proposal, you check to see if the pin is >>>>> "egpio capable" for a pin and if so just sets the bit - muxing it to >>>>> apps (or the island?). >>>> >>>> Right, so if there is a request for a egpio-capable pin, the driver >>>> flips the ownership. Are you suggesting having some kind of checks to determine >>>> who should own it? >>>> >>> >>> I see, I missed that nuance. So Linux will steal any pins that are >>> mentioned in DT. But that would mean that you're relying on someone else >>> to ensure that this bit is cleared for the other pins and you would not >>> be able to explicitly flip the state back to island mode in runtime. >>> >>> I would prefer that this was more explicit. >>> >>>>> It seems reasonable that this would be another pinmux state for these >>>>> pins, rather than just flipping them all in one or the other direction. >>>> >>>> hmm, I don't understand. This is not a pinmux state, its a switch to decide >>>> the ownership. >>> >>> But does it mux the pin to the island, or does it state that the island >>> is now in charge of the associated TLMM registers? >> >> The island processor does not access the APPS TLMM register space, it has its >> own TLMM register space that it configures. APPS TLMM registers control its >> mux/conf settings and Island TLMM registers controls its mux/conf. So essentially >> there are 2 sets of registers to control the same pin. >> This bit is more like a top level mux which decides what register settings >> take affect. >> > > "One mux to rule them all" :) > > When we switch this mux towards the Island TLMM, do we need to configure > the APPS TLMM in a particular way, or does the state of that not matter? No APPS TLMM settings should be needed, the state of that does not matter. > Would it be reasonable to say that when muxed towards the island the > apps should always be in gpio mux with some predetermined properties, to > save power? No, the the register settings in APPS TLMM are nop/dont care when egpio_enable is 0. > To reiterate, as proposed, mentioning a egpio-capable pin in the apps > DTS will cause it to be muxed to the APSS TLMM. But I'm not convinced > that we don't have scenarios where one might want to dynamically mux the > pin between island and apss tlmm. > > My suggestion is that even that it's two independent muxes controlled in > the apps tlmm, we'd express them in the same pinmux, i.e. we'd have > something like: > > some-local-state { > pins = "gpio1"; > function = "gpio"; > output-high; > }; so this would set the function to gpio in the APPS TLMM and set the egpio_enable = 1? which was also what the original $SUBJECT patch did. > some-remote-state { > pins = "gpio1"; > function = "island"; /* or just egpio... ? */ > }; Here we add a new function to the pin and that's used to set the egpio_enable to 0? > One case I imaging where this could be useful is to allow Linux to > configure a known state of pins when the island isn't running, from the > remoteproc driver and then flip it over to island mode before booting > the remote. So we save power during boot up until the island processor comes up? So fwik when we boot linux its either configured to boot the island processor or not. Are you talking about some scenario where the island processor comes up on demand and goes down when not used? -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation