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Subject: Re: [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the
 trace generated
To:     Mathieu Poirier <mathieu.poirier@linaro.org>
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com,
        james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org,
        mike.leach@linaro.org, will@kernel.org, lcherian@marvell.com,
        coresight@lists.linaro.org
References: <20210921134121.2423546-1-suzuki.poulose@arm.com>
 <20210921134121.2423546-4-suzuki.poulose@arm.com>
 <20210930175421.GB3047827@p14s>
 <60037d18-9d0e-68ce-2a34-aa84e7876fb8@arm.com>
 <20211001151535.GA3148492@p14s>
From:   Suzuki K Poulose <suzuki.poulose@arm.com>
Message-ID: <355cae15-9a57-c321-0680-d280b6dbe87e@arm.com>
Date:   Fri, 1 Oct 2021 16:22:02 +0100
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On 01/10/2021 16:15, Mathieu Poirier wrote:
> On Fri, Oct 01, 2021 at 09:36:24AM +0100, Suzuki K Poulose wrote:
>> On 30/09/2021 18:54, Mathieu Poirier wrote:
>>> Hi Suzuki,
>>>
>>> On Tue, Sep 21, 2021 at 02:41:07PM +0100, Suzuki K Poulose wrote:
>>>> We collect the trace from the TRBE on FILL event from IRQ context
>>>> and when via update_buffer(), when the event is stopped. Let us
>>>
>>> s/"and when via"/"and via"
>>>
>>>> consolidate how we calculate the trace generated into a helper.
>>>>
>>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>>> Cc: Mike Leach <mike.leach@linaro.org>
>>>> Cc: Leo Yan <leo.yan@linaro.org>
>>>> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>> ---
>>>>    drivers/hwtracing/coresight/coresight-trbe.c | 48 ++++++++++++--------
>>>>    1 file changed, 30 insertions(+), 18 deletions(-)
>>>>
>>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
>>>> index 63f7edd5fd1f..063c4505a203 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-trbe.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
>>>> @@ -527,6 +527,30 @@ static enum trbe_fault_action trbe_get_fault_act(u64 trbsr)
>>>>    	return TRBE_FAULT_ACT_SPURIOUS;
>>>>    }
>>>> +static unsigned long trbe_get_trace_size(struct perf_output_handle *handle,
>>>> +					 struct trbe_buf *buf,
>>>> +					 bool wrap)
>>>
>>> Stacking
>>>
>>
>> Ack
>>
>>>> +{
>>>> +	u64 write;
>>>> +	u64 start_off, end_off;
>>>> +
>>>> +	/*
>>>> +	 * If the TRBE has wrapped around the write pointer has
>>>> +	 * wrapped and should be treated as limit.
>>>> +	 */
>>>> +	if (wrap)
>>>> +		write = get_trbe_limit_pointer();
>>>> +	else
>>>> +		write = get_trbe_write_pointer();
>>>> +
>>>> +	end_off = write - buf->trbe_base;
>>>
>>> In both arm_trbe_alloc_buffer() and trbe_handle_overflow() the base address is
>>> acquired using get_trbe_base_pointer() but here it is referenced directly - any
>>> reason for that?  It certainly makes reviewing this simple patch quite
>>> difficult because I keep wondering if I am missing something subtle...
>>
>> Very good observation. So far, we always prgrammed the TRBBASER with the
>> the VA(ring_buffer[0]). And thus reading the BASER and using the
>> buf->trbe_base is all fine.
>>
>> But going forward, we are going to use different values for the TRBBASER
>> to work around erratum. Thus to make the computation of the "offsets"
>> within the ring buffer, it is always correct to use this field. I could
>> move this to the patch where the work around is introduced, and put in
>> a comment there.
> 
> That will be greatly appreciated.

I have moved this to the patch, which introduces the concept of "TRBE 
using" a different BASE address than the beginning of the ring buffer.

Thanks
Suzuki