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Subject: Re: [PATCH v3 3/4] x86/mm: Flush global TLB when switching to
 trampoline page-table
From:   =?utf-8?B?SsO2cmcgUsO2ZGVs?= <jroedel@suse.de>
In-Reply-To: <03994224-abba-4551-9f9d-1360af69c78e@intel.com>
Date:   Fri, 1 Oct 2021 19:57:52 +0200
Cc:     x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        hpa@zytor.com, Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Mike Rapoport <rppt@kernel.org>,
        Andrew Morton <akpm@linux-foundation.org>,
        Brijesh Singh <brijesh.singh@amd.com>,
        linux-kernel@vger.kernel.org
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References: <20211001154817.29225-1-joro@8bytes.org>
 <20211001154817.29225-4-joro@8bytes.org>
 <03994224-abba-4551-9f9d-1360af69c78e@intel.com>
To:     Dave Hansen <dave.hansen@intel.com>
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> Am 01.10.2021 um 18:13 schrieb Dave Hansen <dave.hansen@intel.com>:
>=20
> On 10/1/21 8:48 AM, Joerg Roedel wrote:
>> Move the switching code into a function so that it can be re-used and
>> add a global TLB flush. This makes sure that usage of memory which is
>> not mapped in the trampoline page-table is reliably caught.
>=20
> This looks fine.  But, just to be clear, nothing in this series reuses
> the code, right?

Correct, but my SEV-ES kexec series will re-use it, as it also uses the =
trampoline_pgd and switches to real-mode to park the APs.

Regards,

J=C3=B6rg=