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[23.128.96.18]) by mx.google.com with ESMTP id y32si2253596ede.249.2021.10.01.12.30.51; Fri, 01 Oct 2021 12:31:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20210112 header.b=EneX9Nz+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229618AbhJAT2q (ORCPT + 99 others); Fri, 1 Oct 2021 15:28:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229515AbhJAT2n (ORCPT ); Fri, 1 Oct 2021 15:28:43 -0400 Received: from mail-yb1-xb2c.google.com (mail-yb1-xb2c.google.com [IPv6:2607:f8b0:4864:20::b2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01787C061775 for ; Fri, 1 Oct 2021 12:26:57 -0700 (PDT) Received: by mail-yb1-xb2c.google.com with SMTP id s4so6349004ybs.8 for ; Fri, 01 Oct 2021 12:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+I3d1su/KvdHqod/jvZj4lVFL3MuIPfZCays9g7CN7k=; b=EneX9Nz+akqriwHswlfP+5z4mszZUBt5tejoF6pkNPF4ct3GPQNHTy1gLNzJq7fhV5 Q3tNAAhnrbl2HAPqbX8HMMmI1D4l2VwdFNQK1rW1Lu+WxG36WHsJLmeRJ13tN85QPbR6 cyiOz85aw1l/YHU1853UOnyKSoEmVMMIHawKdQUekUrMJZRrAEykcvYaROArZIcTq1uF ptpZKieD7AvZ/dcJtDOtylXMuHp0m7OWsyjH4WX1poQZPbals+M4U4iVxckbt+J3JcjR k1NWIDAsCe9KtV59TJkdQs4MFoiN25XNYfxr1X3qGzMXRl550k6H94RilzZ/fJhr8lE6 5b2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+I3d1su/KvdHqod/jvZj4lVFL3MuIPfZCays9g7CN7k=; b=XMkEZYRmP1Y96bX5/66u6+KUtBQY5M6Ww+kIpH6o8U3P6fC9OpYbmSiYciuiQVCTyw hHUwPCzWgoL14jIrEv7MxUj6s/fJX56O9JH63yxwoNPsNk1KiMJ5SKCQzW+CXFiiJr7y mVdIR6IqoFZjiBQ5gV4iphUjuCbJzECUsD4vSnWgoU8jLp7V2Vw3tbMw3eUaR7KSZFDO euv/TsV4Yn5h0F4Zj178bATxTF6W19DDhmatoRGawVRmPRQvERym3MTzjYprQ1gIUUSj aydT7g8gVeShF3BJ+zMLX0dX7PxiKC4bSkzB3hADMUd+Q+vdEwRnrqse/+dbT+gUFLa7 3h9w== X-Gm-Message-State: AOAM5301ylKcP4he1lzU/IhFfaD3Ap/4bG4clHgaIgC2E2reZ+HktW3h L4/MDh7xQqCowSpQ/wmHrT7jyftqbZnzGrVhPkL5GA== X-Received: by 2002:a25:1dd7:: with SMTP id d206mr5271610ybd.486.1633116416960; Fri, 01 Oct 2021 12:26:56 -0700 (PDT) MIME-Version: 1.0 References: <20210928235635.1348330-1-willmcvicker@google.com> <7766faf8-2dd1-6525-3b9a-8ba790c29cff@canonical.com> In-Reply-To: From: Saravana Kannan Date: Fri, 1 Oct 2021 12:26:20 -0700 Message-ID: Subject: Re: [PATCH v2 00/12] arm64: Kconfig: Update ARCH_EXYNOS select configs To: Olof Johansson Cc: Arnd Bergmann , Geert Uytterhoeven , Will McVicker , Krzysztof Kozlowski , Russell King , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Linus Walleij , Alessandro Zummo , Alexandre Belloni , John Stultz , Thomas Gleixner , Lee Jones , "Cc: Android Kernel" , Linux ARM , Linux Kernel Mailing List , linux-samsung-soc , linux-clk , "open list:GPIO SUBSYSTEM" , linux-rtc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 1, 2021 at 8:27 AM Olof Johansson wrote: > > On Fri, Oct 1, 2021 at 2:01 AM Arnd Bergmann wrote: > > > > On Fri, Oct 1, 2021 at 10:19 AM Geert Uytterhoeven wrote: > > > On Fri, Oct 1, 2021 at 7:24 AM Saravana Kannan wrote: > > > > GIC and arch timer. Basically the minimal kernel would need a timer > > > > for the scheduler tick and IRQ controller to get the timer IRQ and the > > > > fixed clock driver if the archtimer uses one to get its frequency and > > > > the early UART console is pointless as a module (so build it in to > > > > allow debugging/development). > > > > > > > > And then all new drivers, we should make sure are implemented as > > > > tristate drivers. And we can go back and slowly work on converting > > > > existing drivers to modules (community effort -- not one person or > > > > entity) -- at least the ones where the author has hardware or ones > > > > where the change is very likely to be correct and someone else is > > > > willing to test it. We'll never be able to support some/all ARM32 (do > > > > they even have a GIC/arch timer standard?), but at least for ARM64, > > > > this seems like a viable goal. > > > > > > Cortex-A7/A15 and later have GIC and architectured timer, so it should > > > work for contemporary systems. > > > Cortex-A9 systems may have GIC, and TWD and/or Global Timer (but I've > > > seen SoCs where the interrupt for the latter was not wired :-(. > > > > There are a number of well-known examples even with 64-bit chips or > > Cortex-A7/A15 based SoCs that can't use the architected timer, > > irqchip or iommu. > > > > Apple M1, Broadcom BCM283x, Samsung Exynos5 and > > some Hisilicon server parts come to mind, I'm sure there > > are more. > > There's also more and more movement towards having coprocessors with > standardized interfaces dealing with this functionality. We're > currently at the point where they have coprocessors with > non-standardized interfaces, and it's useful to keep encouraging > convergence in this area to everybody's benefit. I don't find it > particularly useful to make life easier for the custom solutions at > the expense of others like this patchset does, when that's (just > beyond? on?) the horizon. > > > > What are the plans for other architectures? > > > I've seen similar patches being applied for e.g. MIPS. > > > > There is some work in the more actively maintained MIPS > > platforms to make those behave more like Arm/powerpc/riscv/m68k > > platforms, using a single image and moving drivers into modules. > > Most MIPS platforms seem unlikely to get updated to this, > > and will continue to require a SoC specific kernel binary forever, > > similar to the renesas superh platforms. Most of the less > > common architectures (arc, csky, hexagon, nios2, xtensa, > > microblaze, nds32, openrisc, sparc/leon) are way behind that > > though, and generally don't work at all without out-of-tree > > code. > > One of the arguments for needing some of these core drivers in-kernel > is that some platforms boot at very conservative DVFS operating > points, to a degree that you really want to turn up the CPU clocks > fairly early during boot. > > If you don't have the drivers built-in, you can't do that and/or you > create possible fragile or awkward inter-module dependencies with > deferred probing, etc. We do care about boot time enough to prefer to > just build them in for this reason. Go look at a Pixel 5, we got this working just fine with all these drivers as modules and we definitely care about boot time. You just need to load your CPU freq driver and the other ones it needs early on. And with fw_devlink=on (default in upstream), there's hardly any deferred probing. > If vmlinux binary size is a concern, maybe it's time to consider > splitting the drivers into a bare-minimum piece that's not a module > for early setup, and the rest that can be loaded post-boot. Isn't this literally what I was suggesting with my ARM64_MINIMAL_GENERIC_KERNEL suggestion? Build in all the bare minimum drivers that are needed before module loading can happen? You'd just select them all under that config. And any existing platform that wants to use it would break up their drivers into modules and switch to it. -Saravana