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dmarc=none action=none header.from=intel.com; Received: from BYAPR11MB3320.namprd11.prod.outlook.com (2603:10b6:a03:18::25) by SJ0PR11MB5037.namprd11.prod.outlook.com (2603:10b6:a03:2ac::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.19; Fri, 1 Oct 2021 23:00:47 +0000 Received: from BYAPR11MB3320.namprd11.prod.outlook.com ([fe80::4167:f9ef:19b2:eaff]) by BYAPR11MB3320.namprd11.prod.outlook.com ([fe80::4167:f9ef:19b2:eaff%3]) with mapi id 15.20.4566.019; Fri, 1 Oct 2021 23:00:47 +0000 Subject: Re: [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall To: Thomas Gleixner , Andy Lutomirski , the arch/x86 maintainers CC: Tony Luck , Dave Hansen , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Jens Axboe , Christian Brauner , "Peter Zijlstra (Intel)" , Shuah Khan , Arnd Bergmann , Jonathan Corbet , Raj Ashok , Jacob Pan , Gayatri Kammela , Zeng Guang , "Williams, Dan J" , Randy E Witt , "Shankar, Ravi V" , Ramesh Thomas , Linux API , , "Linux Kernel Mailing List" , References: <20210913200132.3396598-1-sohil.mehta@intel.com> <20210913200132.3396598-12-sohil.mehta@intel.com> <877dex7tgj.ffs@tglx> <87tui162am.ffs@tglx> <25ba1e1f-c05b-4b67-b547-6b5dbc958a2f@www.fastmail.com> <87pmsp5aqx.ffs@tglx> <0364c572-4bc2-4538-8d65-485dbfa81f0d@www.fastmail.com> <875yug4eos.ffs@tglx> From: Sohil Mehta Message-ID: <410ccb21-49d8-4ec0-3f23-07e37c694bbe@intel.com> Date: Fri, 1 Oct 2021 16:00:44 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.14.0 In-Reply-To: <875yug4eos.ffs@tglx> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-ClientProxiedBy: SJ0PR03CA0292.namprd03.prod.outlook.com (2603:10b6:a03:39e::27) To BYAPR11MB3320.namprd11.prod.outlook.com (2603:10b6:a03:18::25) MIME-Version: 1.0 Received: from [192.168.86.37] (73.222.31.188) by SJ0PR03CA0292.namprd03.prod.outlook.com (2603:10b6:a03:39e::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend Transport; 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We can simply do: > XSAVES(); > fpu.state.xtsate.uintr.uinv = 0; I am a bit confused. Do we need to set UINV to 0 explicitly? If XSAVES gets called twice during context switch then the UINV in the XSTATE buffer automatically gets set to 0. Since XSAVES saves the current UINV value in the MISC_MSR which was already set to 0 by the previous XSAVES. Though, this probably happens due to pure luck than intentional design :) > which allows to do as many XRSTORS in a row as we want. Only the final > one on the way to user space will have to restore the real vector if the > register state is not valid: > > if (fpu_state_valid()) { > if (needs_uinv(current) > wrmsrl(UINV, vector); > } else { > if (needs_uinv(current) > fpu.state.xtsate.uintr.uinv = vector; > XRSTORS(); > } I might have missed some subtle difference. Has this logic changed from what you previously suggested for arch_exit_to_user_mode_prepare()?        if (xrstors_pending)) {             // Update the saved xstate for xrstors             // Unconditionally update the UINV since it could have been overwritten by calling XSAVES twice.                current->xstate.uintr.uinv = UINTR_NOTIFICATION_VECTOR;                 current->xstate.uintr.uirr |= pir;         } else {                 // Manually restore UIRR and UINV                 rdmsrl(IA32_UINTR_RR, uirr);                 wrmsrl(IA32_UINTR_RR, uirr | pir);             misc.val64 = 0;                 misc.uittsz = current->uintr->uittsz;                 misc.uinv = UINTR_NOTIFICATION_VECTOR;                 wrmsrl(IA32_UINTR_MISC, misc.val64);         } > Hmm? The one case I can see this failing is if there was another XRSTORS after the "final" restore in arch_exit_to_user_mode_prepare()? I think that is not possible but I am not an expert on this. Did I misunderstand something? Thanks, Sohil