Received: by 2002:a05:6a10:d5a5:0:0:0:0 with SMTP id gn37csp4068051pxb; Mon, 4 Oct 2021 16:41:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlsA/5n7bfLH9Dat3QB7NV039cQz7EdA6s1pDdrSzRRWsVNWsChtETgXNlM2A5zQmg+b6A X-Received: by 2002:a17:906:2882:: with SMTP id o2mr21587901ejd.459.1633390872441; Mon, 04 Oct 2021 16:41:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633390872; cv=none; d=google.com; s=arc-20160816; b=t7C4Q4C09aBxkgiktVIzs55VDINjYQrR8Lxi2r4przUxjRtfsl0JFbiTN7qXZQdigT m0syQBfxrFRgMLog2J8tou+MO1a+o55WNWsa15ZQpJdUdvWXEH/AOmtmJ382fBhtPd53 866VJ/9c5LOL7uRgvi0OleAIqtFg6KarzcpO3ZF3kKlDMUIa1Dypc9fYgMWS5lfI6BVa Y2aVDiAzlfPBwBblmevWDEqbd1cl0CQDiLZ09fKh9Dwr3RiltC0gjmNoAsVCxk59N+b8 vftPLIviJ+P0i4qtLAOya4s7yIFBC48VZH8f1O1LGLiXNtlrCXE2MEbHZ8MvpyR3v+vW Wn4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=wN77pUz9wWmtPW1Ow7RCFc3sZndMnPvR9NrcBh6B7g4=; b=Wp44Zp46wZlF/Fwe+pfN5zE08v07SvfnKf6psGNi+cEGXB2XL9B2DHFRsXvAO+lEoe 4uB/LHa7soBaE666AY6se/v3rZkYf/8UeLKPX2+Ft2zlxl1TfkMTiAiKVMuvMuAi/3LL 4wH9B6WnJ+MSxDzmSu8pbRoRM4IGggsvz9PUhxY92zCQoUYg77AXpf1uGC0g4qpLT/4y jkw6cYjt8rdKkNauS/Zr6pJH4cSMt5rcZ2syS/S1OvJW8LBu8fYAQlhCSGaDbn/3QVBr fJoiJDi+oIrPb8uoJPg4FOHjtcbsUmtVXiXM4s94FKJzvSwK1bJxRAMl9ePPgm4++ZsX qnMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JvNxsoxP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q11si18349041edv.274.2021.10.04.16.40.49; Mon, 04 Oct 2021 16:41:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=JvNxsoxP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234850AbhJDTxr (ORCPT + 99 others); Mon, 4 Oct 2021 15:53:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:46696 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234691AbhJDTxo (ORCPT ); Mon, 4 Oct 2021 15:53:44 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 79BF4610A5; Mon, 4 Oct 2021 19:51:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633377115; bh=ftIISwj5VomvNZxJNk+YRaZbhRwimc0N+dZ0U1M/kNM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=JvNxsoxP0lBgAXvh4kDSdCWDVFWoqH3CZyIVwRdbN7aUKBCGwK7qvedJ1TbprIUUQ 9e2LPSbyQhdhMwzdvy58yqhrF29wamamie7tgj+7gVfOGNMZClu+Sv/99vbJDKuEu1 kCnTurgGjhCYj4/fl3VdxWRl9gUZmC3TGJj/w1U+C3JzL5Gyadwt/XoJ9L1Iqd9ZEv HTgjjhAaxCbNiD7bpQyiSk/AtOyUOgMvrLPeyHtWlTB8ybVbh/qhvBTCfJRnOv56O7 hDD6u3Q6FfDaOBP+lSTJygSjbFTQhKX6reAE/WBze8Py/cG5+fLKY0TRvJmVkrKvyk rKZP2qmbV2ZUw== Received: by mail-ed1-f49.google.com with SMTP id b8so34757224edk.2; Mon, 04 Oct 2021 12:51:55 -0700 (PDT) X-Gm-Message-State: AOAM533mAr1R6PLSK+klJbK2lH6IHC4oAtROvH9D6g815cN0hi/EgK4b 6NUXVxDRntLjUBmlPlZElF0xR/ycz7LT6KZukw== X-Received: by 2002:a17:906:7217:: with SMTP id m23mr19125282ejk.466.1633377114021; Mon, 04 Oct 2021 12:51:54 -0700 (PDT) MIME-Version: 1.0 References: <20210929163847.2807812-1-maz@kernel.org> <20211004083845.GA22336@lpieralisi> In-Reply-To: <20211004083845.GA22336@lpieralisi> From: Rob Herring Date: Mon, 4 Oct 2021 14:51:39 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 00/14] PCI: Add support for Apple M1 To: Lorenzo Pieralisi Cc: Marc Zyngier , devicetree@vger.kernel.org, "linux-kernel@vger.kernel.org" , PCI , Bjorn Helgaas , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Alyssa Rosenzweig , Stan Skowronek , Mark Kettenis , Sven Peter , Hector Martin , Robin Murphy , Joey Gouly , Joerg Roedel , Android Kernel Team Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 4, 2021 at 3:38 AM Lorenzo Pieralisi wrote: > > On Wed, Sep 29, 2021 at 05:38:33PM +0100, Marc Zyngier wrote: > > This is v5 of the series adding PCIe support for the M1 SoC. Not a lot > > has changed this time around, and most of what I was saying in [1] is > > still valid. > > > > Very little has changed code wise (a couple of bug fixes). The series > > however now carries a bunch of DT updates so that people can actually > > make use of PCIe on an M1 box (OK, not quite, you will still need [2], > > or whatever version replaces it). The corresponding bindings are > > either already merged, or queued for 5.16 (this is the case for the > > PCI binding). > > > > It all should be in a state that makes it mergeable (yeah, I said that > > last time... I mean it this time! ;-). > > > > As always, comments welcome. > > > > M. > > > > [1] https://lore.kernel.org/r/20210922205458.358517-1-maz@kernel.org > > [2] https://lore.kernel.org/r/20210921222956.40719-2-joey.gouly@arm.com > > > > Alyssa Rosenzweig (2): > > PCI: apple: Add initial hardware bring-up > > PCI: apple: Set up reference clocks when probing > > > > Marc Zyngier (10): > > irqdomain: Make of_phandle_args_to_fwspec generally available > > of/irq: Allow matching of an interrupt-map local to an interrupt > > controller > > PCI: of: Allow matching of an interrupt-map local to a PCI device > > PCI: apple: Add INTx and per-port interrupt support > > PCI: apple: Implement MSI support > > iommu/dart: Exclude MSI doorbell from PCIe device IOVA range > > PCI: apple: Configure RID to SID mapper on device addition > > arm64: dts: apple: t8103: Add PCIe DARTs > > arm64: dts: apple: t8103: Add root port interrupt routing > > arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address > > > > Mark Kettenis (2): > > arm64: apple: Add pinctrl nodes > > arm64: apple: Add PCIe node > > > > MAINTAINERS | 7 + > > arch/arm64/boot/dts/apple/t8103-j274.dts | 23 + > > arch/arm64/boot/dts/apple/t8103.dtsi | 203 ++++++ > > drivers/iommu/apple-dart.c | 27 + > > drivers/of/irq.c | 17 +- > > drivers/pci/controller/Kconfig | 17 + > > drivers/pci/controller/Makefile | 1 + > > drivers/pci/controller/pcie-apple.c | 822 +++++++++++++++++++++++ > > drivers/pci/of.c | 10 +- > > include/linux/irqdomain.h | 4 + > > kernel/irq/irqdomain.c | 6 +- > > 11 files changed, 1127 insertions(+), 10 deletions(-) > > create mode 100644 drivers/pci/controller/pcie-apple.c > > I have applied (with very minor log changes) patches [1-9] to > pci/apple for v5.16, I expect the dts changes to go via the > arm-soc tree separately, please let me know if that works for you. FYI, I pushed patches 1-3 to kernelCI and didn't see any regressions. I am a bit worried about changes to the DT interrupt parsing and ancient platforms (such as PowerMacs). Most likely there wouldn't be any report until -rc1 or months later on those old systems. Rob