Received: by 2002:a05:6a10:d5a5:0:0:0:0 with SMTP id gn37csp4792455pxb; Tue, 5 Oct 2021 10:23:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxvDLcVZR8JGpNyG500sfMI1diCyIJIGoahmc2lKJYE9dW5AAxhA3J08K/znL2GcqFRHYFi X-Received: by 2002:a17:906:3054:: with SMTP id d20mr25721636ejd.294.1633454622230; Tue, 05 Oct 2021 10:23:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633454622; cv=none; d=google.com; s=arc-20160816; b=t6kSC/8mY4kAKAVZu5ao10NcIi72yqaBcRIOhd4olPuD6f9D7WE5wsXBuhZInICmtm p3MHQeffov4RWhBPMwyB63f4jpzrQijbix68NJCQxC//qWxWU6fKha0zA1liYq9celOI 8gvzPfZFECrLgZcb8iDqIZuw6hpnFHlwF5ot7L/bNNDxJ528M38fn8KN7qnG/MYs3x5y 6vtWOlnsofcCseMhMNuVo9ilqYoAfGbkHgVcUx1yuznH5v8WMhIDe1ZGHsGWtS53GtDj CMoXNapC7kPNQVgPoUJl0GUhY2rSQN6EzABFdeAPNM08khCwxyMIvzYVWRKtbIbjgXk8 AHUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=N47+TPA/zkw9hAibtj7P4+4WGvQNRkSWW1Y93z3mdEw=; b=y/9msowHkdeWdikZmx0s00Qik/lMNZOb25eoXMr3UDgkmYrv9srCg5Kim94GpEm3e3 /7ilqb3imvbvTc0eKzNECpzFQSfb3gVuDIV5VBBjA361KOEHuB6si5DD6LUcEHwS1tT6 8HNI0HM4cSk3BOy4EA4IJb9a5vn5ojgqVHwKquZMW/Z8Kja56QHWAzLcT1XKZ5rYlsGk PuBailasB3dXCbzXQliBCMMaw67apdIxH0JqulP0TiDpN6okxSPy7rtOVzHFaaOC2QyO YHQredUzZRLD2yQBflm9ofmvdOE+Q/T8ABTB5CbviCCQ5NKRNw6Sgps6zVeUiUUMbQv/ vARA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id gn42si8072210ejc.441.2021.10.05.10.23.17; Tue, 05 Oct 2021 10:23:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236778AbhJERTV (ORCPT + 99 others); Tue, 5 Oct 2021 13:19:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:56670 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234938AbhJERTU (ORCPT ); Tue, 5 Oct 2021 13:19:20 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1C0406124C; Tue, 5 Oct 2021 17:17:27 +0000 (UTC) From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org, Pingfan Liu Cc: Will Deacon , "Paul E. McKenney" , Thomas Gleixner , linux-kernel@vger.kernel.org, Mark Rutland , Yuichi Ito , Julien Thierry , Marc Zyngier , Joey Gouly , Sami Tolvanen Subject: Re: [PATCHv4 0/3] arm64/irqentry: remove duplicate housekeeping of rcu Date: Tue, 5 Oct 2021 18:17:25 +0100 Message-Id: <163345423700.2001694.5653085141940230637.b4-ty@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211001144406.7719-1-kernelfans@gmail.com> References: <20211001144406.7719-1-kernelfans@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 1 Oct 2021 22:44:03 +0800, Pingfan Liu wrote: > When an IRQ is taken, some accounting needs to be performed to enter and > exit IRQ context around the IRQ handler. Historically arch code would > leave this to the irqchip or core IRQ code, but these days we want this > to happen in exception entry code, and architectures such as arm64 do > this. > > Currently handle_domain_irq() performs this entry/exit accounting, and > if used on an architecture where the entry code also does this, the > entry/exit accounting will be performed twice per IRQ. This is > problematic as core RCU code such as rcu_is_cpu_rrupt_from_idle() > depends on this happening once per IRQ, and will not detect quescent > periods correctly, leading to stall warnings. > > [...] Applied to arm64 (for-next/fixes), thanks! [1/3] kernel/irq: make irq_{enter,exit}() in handle_domain_irq() arch optional https://git.kernel.org/arm64/c/db795cf55b21 [2/3] arm64: entry: refactor EL1 interrupt entry logic https://git.kernel.org/arm64/c/ad0d5cfb9535 [3/3] arm64: entry: avoid double-accounting IRQ RCU entry https://git.kernel.org/arm64/c/12074b059fdc -- Catalin