Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Paul Boddie <paul@boddie.org.uk>
To:     Paul Cercueil <paul@crapouillou.net>
Cc:     "H. Nikolaus Schaller" <hns@goldelico.com>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Kees Cook <keescook@chromium.org>,
        "Eric W. Biederman" <ebiederm@xmission.com>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Andrzej Hajda <a.hajda@samsung.com>,
        Neil Armstrong <narmstrong@baylibre.com>,
        Robert Foss <robert.foss@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        Ezequiel Garcia <ezequiel@collabora.com>,
        Harry Wentland <harry.wentland@amd.com>,
        Sam Ravnborg <sam@ravnborg.org>,
        Maxime Ripard <maxime@cerno.tech>,
        Hans Verkuil <hverkuil-cisco@xs4all.nl>,
        Liam Girdwood <lgirdwood@gmail.com>,
        Mark Brown <broonie@kernel.org>, devicetree@vger.kernel.org,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        letux-kernel@openphoenux.org, Jon as Karlman <jonas@kwiboo.se>,
        dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers
Date:   Tue, 05 Oct 2021 23:44:12 +0200
Message-ID: <3514743.EH6qe8WxYI@jason>
In-Reply-To: <O7VI0R.CRIG8R7O0OOI3@crapouillou.net>
References: <cover.1633436959.git.hns@goldelico.com> <c243176cb5e5a3ab5df1fe77f9246b6d5ec4f88e.1633436959.git.hns@goldelico.com> <O7VI0R.CRIG8R7O0OOI3@crapouillou.net>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="iso-8859-1"
Precedence: bulk

On Tuesday, 5 October 2021 22:50:12 CEST Paul Cercueil wrote:
> Hi Nikolaus & Paul,
>=20
> Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller=20
<hns@goldelico.com> a =E9crit :
> >=20
> > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > index 9e34f433b9b5..c3c18a59c377 100644
> > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 {
> >=20
> >  		status =3D "disabled";
> >  =09
> >  	};
> >=20
> > +	hdmi: hdmi@10180000 {
> > +		compatible =3D "ingenic,jz4780-dw-hdmi";
> > +		reg =3D <0x10180000 0x8000>;
> > +		reg-io-width =3D <4>;
> > +
> > +		clocks =3D <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
> > +		clock-names =3D "iahb", "isfr";
> > +
> > +		assigned-clocks =3D <&cgu JZ4780_CLK_HDMI>;
> > +		assigned-clock-rates =3D <27000000>;
>=20
> Any reason why this is set to 27 MHz? Is it even required? Because with
> the current ci20.dts, it won't be clocked at anything but 48 MHz.

EXCLK will be 48MHz, but the aim is to set the HDMI peripheral clock to 27M=
Hz,=20
which is supposedly required. I vaguely recall a conversation about whether=
 we=20
were doing this right, but I don't recall any conclusion.

> > +
> > +		interrupt-parent =3D <&intc>;
> > +		interrupts =3D <3>;
> > +
> > +		/* ddc-i2c-bus =3D <&i2c4>; */
> > +
> > +		status =3D "disabled";
> > +	};
> > +
> > +	lcdc0: lcdc0@13050000 {
> > +		compatible =3D "ingenic,jz4780-lcd";
> > +		reg =3D <0x13050000 0x1800>;
> > +
> > +		clocks =3D <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
> > +		clock-names =3D "lcd", "lcd_pclk";
> > +
> > +		interrupt-parent =3D <&intc>;
> > +		interrupts =3D <31>;
> > +
> > +		status =3D "disabled";
>=20
> I think you can keep lcdc0 enabled by default (not lcdc1 though), since
> it is highly likely that you'd want that.

As far as I know, the clock gating for the LCD controllers acts like a seri=
es=20
circuit, meaning that they both need to be enabled. Some testing seemed to=
=20
confirm this. Indeed, I seem to remember only enabling one clock and not=20
getting any output until I figured this weird arrangement out.

Paul