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Wed, 6 Oct 2021 06:38:41 +0000 (GMT) Subject: Re: [PATCH 2/4] perf: Add mem_hops field in perf_mem_data_src structure To: Peter Zijlstra Cc: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, mingo@redhat.com, acme@kernel.org, jolsa@kernel.org, namhyung@kernel.org, ak@linux.intel.com, linux-perf-users@vger.kernel.org, maddy@linux.ibm.com, atrajeev@linux.vnet.ibm.com, rnsastry@linux.ibm.com, yao.jin@linux.intel.com, ast@kernel.org, daniel@iogearbox.net, songliubraving@fb.com, kan.liang@linux.intel.com, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, paulus@samba.org References: <20211005091837.250044-1-kjain@linux.ibm.com> <20211005091837.250044-2-kjain@linux.ibm.com> <20211005202015.GC174703@worktop.programming.kicks-ass.net> From: kajoljain Message-ID: Date: Wed, 6 Oct 2021 12:08:40 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211005202015.GC174703@worktop.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Qp_ZlBVIm8yGc52uAbjAt6CMtcMq5gLK X-Proofpoint-ORIG-GUID: C7MqGast4V9sEP159Y066WwXnsHTlz3P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-05_06,2021-10-04_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110060040 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/6/21 1:50 AM, Peter Zijlstra wrote: > On Tue, Oct 05, 2021 at 02:48:35PM +0530, Kajol Jain wrote: >> Going forward, future generation systems can have more hierarchy >> within the chip/package level but currently we don't have any data source >> encoding field in perf, which can be used to represent this level of data. >> >> Add a new field called 'mem_hops' in the perf_mem_data_src structure >> which can be used to represent intra-chip/package or inter-chip/off-package >> details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value >> can be used to present different hop levels data. >> >> Also add corresponding macros to define mem_hop field values >> and shift value. >> >> Currently we define macro for HOPS_0 which corresponds >> to data coming from another core but same chip. >> >> For ex: Encodings for mem_hops fields with L2 cache: >> >> L2 - local L2 >> L2 | REMOTE | HOPS_0 - remote core, same chip L2 > > Can we do s/chip/node/ ? Hops are something NUMA related, while chips > come in a bag or something :-) Hi Peter, Sure, I will make this change in next version of this patch-set. Thanks, Kajol Jain > >> +/* hop level */ >> +#define PERF_MEM_HOPS_0 0x01 /* remote core, same chip */ >> +/* 2-7 available */ >> +#define PERF_MEM_HOPS_SHIFT 43