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Wed, 06 Oct 2021 04:31:13 -0700 (PDT) MIME-Version: 1.0 References: <20210825221600.1498939-1-bjorn.andersson@linaro.org> In-Reply-To: <20210825221600.1498939-1-bjorn.andersson@linaro.org> From: Robert Foss Date: Wed, 6 Oct 2021 13:31:02 +0200 Message-ID: Subject: Re: [PATCH] arm64: dts: qcom: sm8350: Add CPU topology and idle-states To: Bjorn Andersson Cc: Andy Gross , Rob Herring , MSM , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 26 Aug 2021 at 00:14, Bjorn Andersson wrote: > > Add CPU topology and define the idle states for the silver and gold > cores as well as the cluster. > > Signed-off-by: Bjorn Andersson > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 141 +++++++++++++++++++++++++++ > 1 file changed, 141 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index c6e1febaee46..35e8935bc1fa 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -48,6 +48,8 @@ CPU0: cpu@0 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD0>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_0: l2-cache { > compatible = "cache"; > @@ -65,6 +67,8 @@ CPU1: cpu@100 { > enable-method = "psci"; > next-level-cache = <&L2_100>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_100: l2-cache { > compatible = "cache"; > @@ -79,6 +83,8 @@ CPU2: cpu@200 { > enable-method = "psci"; > next-level-cache = <&L2_200>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD2>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_200: l2-cache { > compatible = "cache"; > @@ -93,6 +99,8 @@ CPU3: cpu@300 { > enable-method = "psci"; > next-level-cache = <&L2_300>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD3>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_300: l2-cache { > compatible = "cache"; > @@ -107,6 +115,8 @@ CPU4: cpu@400 { > enable-method = "psci"; > next-level-cache = <&L2_400>; > qcom,freq-domain = <&cpufreq_hw 1>; > + power-domains = <&CPU_PD4>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_400: l2-cache { > compatible = "cache"; > @@ -121,6 +131,8 @@ CPU5: cpu@500 { > enable-method = "psci"; > next-level-cache = <&L2_500>; > qcom,freq-domain = <&cpufreq_hw 1>; > + power-domains = <&CPU_PD5>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_500: l2-cache { > compatible = "cache"; > @@ -136,6 +148,8 @@ CPU6: cpu@600 { > enable-method = "psci"; > next-level-cache = <&L2_600>; > qcom,freq-domain = <&cpufreq_hw 1>; > + power-domains = <&CPU_PD6>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_600: l2-cache { > compatible = "cache"; > @@ -150,12 +164,86 @@ CPU7: cpu@700 { > enable-method = "psci"; > next-level-cache = <&L2_700>; > qcom,freq-domain = <&cpufreq_hw 2>; > + power-domains = <&CPU_PD7>; > + power-domain-names = "psci"; > #cooling-cells = <2>; > L2_700: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > }; > }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + > + core4 { > + cpu = <&CPU4>; > + }; > + > + core5 { > + cpu = <&CPU5>; > + }; > + > + core6 { > + cpu = <&CPU6>; > + }; > + > + core7 { > + cpu = <&CPU7>; > + }; > + }; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "silver-rail-power-collapse"; > + arm,psci-suspend-param = <0x40000004>; > + entry-latency-us = <355>; > + exit-latency-us = <909>; > + min-residency-us = <3934>; > + local-timer-stop; > + }; > + > + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "gold-rail-power-collapse"; > + arm,psci-suspend-param = <0x40000004>; > + entry-latency-us = <241>; > + exit-latency-us = <1461>; > + min-residency-us = <4488>; > + local-timer-stop; > + }; > + }; > + > + domain-idle-states { > + CLUSTER_SLEEP_0: cluster-sleep-0 { > + compatible = "domain-idle-state"; > + idle-state-name = "cluster-power-collapse"; > + arm,psci-suspend-param = <0x4100c344>; > + entry-latency-us = <3263>; > + exit-latency-us = <6562>; > + min-residency-us = <9987>; > + local-timer-stop; > + }; > + }; > }; > > firmware { > @@ -179,6 +267,59 @@ pmu { > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > + > + CPU_PD0: cpu0 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; > + }; > + > + CPU_PD1: cpu1 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; > + }; > + > + CPU_PD2: cpu2 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; > + }; > + > + CPU_PD3: cpu3 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; > + }; > + > + CPU_PD4: cpu4 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&BIG_CPU_SLEEP_0>; > + }; > + > + CPU_PD5: cpu5 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&BIG_CPU_SLEEP_0>; > + }; > + > + CPU_PD6: cpu6 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&BIG_CPU_SLEEP_0>; > + }; > + > + CPU_PD7: cpu7 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&BIG_CPU_SLEEP_0>; > + }; > + > + CLUSTER_PD: cpu-cluster0 { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_SLEEP_0>; > + }; > }; > > reserved_memory: reserved-memory { This looks good to me, and introduces no new issues to dtbs_check. Reviewed-by: Robert Foss