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[23.128.96.18]) by mx.google.com with ESMTP id k25si29009225edf.34.2021.10.06.06.25.49; Wed, 06 Oct 2021 06:26:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=n6hubWn5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238842AbhJFN0B (ORCPT + 99 others); Wed, 6 Oct 2021 09:26:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238923AbhJFNZk (ORCPT ); Wed, 6 Oct 2021 09:25:40 -0400 Received: from mail-oo1-xc35.google.com (mail-oo1-xc35.google.com [IPv6:2607:f8b0:4864:20::c35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE3A3C061753 for ; Wed, 6 Oct 2021 06:23:34 -0700 (PDT) Received: by mail-oo1-xc35.google.com with SMTP id l8-20020a4ae2c8000000b002b5ec765d9fso812755oot.13 for ; Wed, 06 Oct 2021 06:23:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=HIxpcPjjliDmNMsnuequZ0gFoYJjA+Pd57/rdj42aTk=; b=n6hubWn5AXF/sSj8MUZBeNdimUtLnR1jd7Gowh5bUbbHNEgTO1dd3wn5ZW/d5oCTmK nj6lavmhbq/1FojrFBMVYVckHnWUYi/xWSQpEzKh/4zr/n9ZCXz6JNaIra7xNErSt5dY ro8MOAGeDt+hNJ5jMuYaNhKQOEd/0NX+ZSsHwicj4JG+bWCC5MKzNy6prOp0cg5twf/S gy8hC/v3eQjgYdbu0LWCzfk8YW919QfKDO7aRU9jI98z0QYhsUrOBOK2AN4pOr30IBD2 duYoa9Z6jrQrrNZsLXABUrtGiNsqlzhjYRfZ5qIo1XpWFUp46UpdoG5hZN2cQu9q0BFn wcfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=HIxpcPjjliDmNMsnuequZ0gFoYJjA+Pd57/rdj42aTk=; b=Td55dFiAvEcO9sg7aiNDseirBZOXBKVdadKfhlFLG4H8uZhKwapszMUIGekSqzSr5D /sIKRm5KcULq0uui6c7/2E5VL+LCA3nmmooPAv2JNeWfIUpBJ+1qvOdsmXlp+JFFk1+a KxczwNCF+B5eQX9h0U+XNcM8wJdXRw/YgbXk02u6+kpXdzzEOE414T3X211JJCWavT// JSE6Ez1jmV491heITc0sNGstfSGnQ4qnP4icvCLPZXECN45ojxUrlxyZTlkfBLu3VC7r CbG1EFEHac7ro4qHJcZBzPDZfRZxGD2wtBYG4A+kLWU2o2c8nXsLLIlZ5PsF/yfU8m/l 3c5g== X-Gm-Message-State: AOAM532sWy88EOUMyFi9SLuuUudxg6WX2eZf80OP9L1RAK3P36Z36goE t9Gs9wgobxP//ZcChGWR4nZMlHsrKUDWuJVmn0U= X-Received: by 2002:a4a:a6c6:: with SMTP id i6mr17948100oom.73.1633526614154; Wed, 06 Oct 2021 06:23:34 -0700 (PDT) MIME-Version: 1.0 References: <8bbacd0e-4580-3194-19d2-a0ecad7df09c@molgen.mpg.de> In-Reply-To: From: Alex Deucher Date: Wed, 6 Oct 2021 09:23:22 -0400 Message-ID: Subject: Re: `AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y` causes AMDGPU to fail on Ryzen: amdgpu: SME is not compatible with RAVEN To: Borislav Petkov Cc: Paul Menzel , Tom Lendacky , Thomas Gleixner , Ingo Molnar , X86 ML , Dave Hansen , Andy Lutomirski , Peter Zijlstra , LKML , amd-gfx list Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 6, 2021 at 5:42 AM Borislav Petkov wrote: > > On Tue, Oct 05, 2021 at 10:48:15AM -0400, Alex Deucher wrote: > > It's not incompatible per se, but SEM requires the IOMMU be enabled > > because the C bit used for encryption is beyond the dma_mask of most > > devices. If the C bit is not set, the en/decryption for DMA doesn't > > occur. So you need IOMMU to be enabled in remapping mode to use SME > > with most devices. Raven has further requirements in that it requires > > IOMMUv2 functionality to support some features which currently uses a > > direct mapping in the IOMMU and hence the C bit is not properly > > handled. > > So lemme ask you this: do Raven-containing systems exist out there which > don't have IOMMUv2 functionality and which can cause boot failures when > SME is enabled in the kernel .config? There could be some OEM systems that disable the IOMMU on the platform and don't provide a switch in the bios to enable it. The GPU driver will still work in that case, it will just not be able to enable KFD support for ROCm compute. SME won't work for most devices in that case however since most devices have a DMA mask too small to handle the C bit for encryption. SME should be dependent on IOMMU being enabled. > > IOW, can we handle this at boot time properly, i.e., disable SME if we > detect Raven or IOMMUv2 support is missing? > > If not, then we really will have to change the default. I'm not an SME expert, but I thought that that was already the case. We just added the error condition in the GPU driver to prevent the driver from loading when the user forced SME on. IIRC, there were users that cared more about SME than graphics support. Alex > > Thx. > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette