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Subject: Re: `AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y` causes AMDGPU to fail on
 Ryzen: amdgpu: SME is not compatible with RAVEN
To:     Borislav Petkov <bp@alien8.de>,
        Alex Deucher <alexdeucher@gmail.com>
Cc:     Tom Lendacky <thomas.lendacky@amd.com>,
        Paul Menzel <pmenzel@molgen.mpg.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, X86 ML <x86@kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        LKML <linux-kernel@vger.kernel.org>,
        amd-gfx list <amd-gfx@lists.freedesktop.org>
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From:   =?UTF-8?Q?Christian_K=c3=b6nig?= <ckoenig.leichtzumerken@gmail.com>
Message-ID: <d3001b64-7b31-a0ab-d7d9-44b145d412f2@gmail.com>
Date:   Thu, 7 Oct 2021 08:14:18 +0200
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Am 06.10.21 um 21:32 schrieb Borislav Petkov:
> On Wed, Oct 06, 2021 at 02:21:40PM -0400, Alex Deucher wrote:
>> And just another general comment, swiotlb + bounce buffers isn't
>> really useful on GPUs.  You may have 10-100s of MBs of memory mapped
>> long term into the GPU's address space for random access.  E.g., you
>> may have buffers in system memory that the display hardware is
>> actively scanning out of.  For GPUs you should really only enable SME
>> if IOMMU is enabled in remapping mode.  But that is probably beyond
>> the discussion here.
> Right, but insights into how these things work (or don't work) together
> are always welcome. And yes, as 2cc13bb4f59f says:
>
>      "... The bounce buffer
>      code has an upper limit of 256kb for the size of DMA
>      allocations, which is too small for certain devices and
>      causes them to fail."

To make the matter even worse, bounce buffers don't work with APIs like 
Vulkan and some OpenGL/OpenCL extensions.

In those APIs or extensions the assumption is that you can malloc() 
memory in userspace, give the pointer to the kernel driver and have 
coherent access with your device and the CPU at the same time.

In other words you don't even get the chance to bounce the buffers 
between CPU and device access because they are accessed by both at the 
same time.

Regards,
Christian.