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From:   Ryan Chen <ryan_chen@aspeedtech.com>
To:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, Joel Stanley <joel@jms.id.au>,
        Andrew Jeffery <andrew@aj.id.au>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCHv3] clk:aspeed:Fix AST2600 hpll calculate formula
Thread-Topic: [PATCHv3] clk:aspeed:Fix AST2600 hpll calculate formula
Thread-Index: AQHXsbRv6xuXpttuYkWAu3oZNdj4AqvHOzbg
Date:   Thu, 7 Oct 2021 07:45:48 +0000
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Hello Joel,
	Do you have time check this path?

Ryan Chen

Tel : 886-3-5751185 ext:8857

> -----Original Message-----
> From: Ryan Chen <ryan_chen@aspeedtech.com>
> Sent: Saturday, September 25, 2021 10:24 AM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Joel Stanley
> <joel@jms.id.au>; Andrew Jeffery <andrew@aj.id.au>;
> linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCHv3] clk:aspeed:Fix AST2600 hpll calculate formula
>=20
> v2 -> v3: change else than if to directly else if
> v1 -> v2: add Fixes commit hash
>=20
> AST2600 HPLL calculate formula [SCU200]
> HPLL Numerator(M): have fixed value depend on SCU strap.
> M =3D SCU500[10] ? 0x5F : SCU500[8] ? 0xBF : SCU200[12:0]
>=20
> if SCU500[10] =3D 1, M=3D0x5F.
> else if SCU500[10]=3D0 & SCU500[8]=3D1, M=3D0xBF.
> others (SCU510[10]=3D0 and SCU510[8]=3D0)
> depend on SCU200[12:0] (default 0x8F) register setting.
>=20
> HPLL Denumerator (N) =3D  SCU200[18:13] (default 0x2)
> HPLL Divider (P)         =3D      SCU200[22:19] (default 0x0)
>=20
> Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  drivers/clk/clk-ast2600.c | 28 +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
>=20
> diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index
> 085d0a18b2b6..d30188355aaf 100644
> --- a/drivers/clk/clk-ast2600.c
> +++ b/drivers/clk/clk-ast2600.c
> @@ -169,6 +169,32 @@ static const struct clk_div_table ast2600_div_table[=
]
> =3D {  };
>=20
>  /* For hpll/dpll/epll/mpll */
> +static struct clk_hw *ast2600_calc_hpll(const char *name, u32 val) {
> +	unsigned int mult, div;
> +	u32 hwstrap =3D readl(scu_g6_base + ASPEED_G6_STRAP1);
> +
> +	if (val & BIT(24)) {
> +		/* Pass through mode */
> +		mult =3D div =3D 1;
> +	} else {
> +		/* F =3D 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
> +		u32 m =3D val  & 0x1fff;
> +		u32 n =3D (val >> 13) & 0x3f;
> +		u32 p =3D (val >> 19) & 0xf;
> +
> +		if (hwstrap & BIT(10))
> +			m =3D 0x5F;
> +		else if (hwstrap & BIT(8))
> +			m =3D 0xBF;
> +
> +		mult =3D (m + 1) / (n + 1);
> +		div =3D (p + 1);
> +	}
> +	return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
> +			mult, div);
> +};
> +
>  static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)  {
>  	unsigned int mult, div;
> @@ -716,7 +742,7 @@ static void __init aspeed_g6_cc(struct regmap *map)
>  	 * and we assume that it is enabled
>  	 */
>  	regmap_read(map, ASPEED_HPLL_PARAM, &val);
> -	aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] =3D ast2600_calc_pll("hpll",
> val);
> +	aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] =3D ast2600_calc_hpll("hpll",
> +val);
>=20
>  	regmap_read(map, ASPEED_MPLL_PARAM, &val);
>  	aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] =3D ast2600_calc_pll("mpll",
> val);
> --
> 2.17.1