Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Anup Patel <anup.patel@wdc.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>,
        Palmer Dabbelt <palmerdabbelt@google.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Rob Herring <robh+dt@kernel.org>
Cc:     Atish Patra <atish.patra@wdc.com>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Anup Patel <anup@brainfault.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
        Bin Meng <bmeng.cn@gmail.com>
Subject: [RFC PATCH v4 05/10] dt-bindings: interrupt-controller: Add ACLINT MSWI and SSWI bindings
Date:   Thu,  7 Oct 2021 18:06:27 +0530
Message-Id: <20211007123632.697666-6-anup.patel@wdc.com>
In-Reply-To: <20211007123632.697666-1-anup.patel@wdc.com>
References: <20211007123632.697666-1-anup.patel@wdc.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
WDCIPOUTBOUND: EOP-TRUE
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4nCTDqACoDUW+YGUyaZZ18/fNC3kmURcBrIB//8JK1tsfTiUhtzXb5guj/b1?=
 =?us-ascii?Q?ksYh+VtL/i4esyUZW/6uv6C0o/7ZgQH3jQ/twFMBRClbG67c9aKJjmMPfGsn?=
 =?us-ascii?Q?8yp3x8rSGTM2E8TUV8EF4BJGDzHi7msiW2utFaongjWMn9EXT6tvlBZ0viAb?=
 =?us-ascii?Q?HZJpGVbaLs8bgPJcTdBfbn7AFRewu9uwIqSg9r4/iu+4FkMjbxr6ULuSbiD7?=
 =?us-ascii?Q?RgtmdhJgIZUjdOjEGev+YSsaC1Ra8L2aNLJQWENE6D7hewrUGgiLRsAjjK5y?=
 =?us-ascii?Q?sJ7sEj3bbYxHCnAPA/+eKh1rLY87tMdOV/rW1r/TbO23xDTJ1clj4SfErWWl?=
 =?us-ascii?Q?u1JwB98C236AnXGrYlcS6mKOhglNciKsGr99WZG7nBtAU6qdvED55toVuH4M?=
 =?us-ascii?Q?Gx0MBTQhsyhcuSFwZZ/GZTCpErZ7NK/5zBMdnAcR2HIt8TnNHfcjooaw+Ta5?=
 =?us-ascii?Q?4XYhxKIphWOw95ftkOS0B97qqi12cJxc+5ACsZoFIaC4aRSDAYthm/79N0hF?=
 =?us-ascii?Q?RrL0gCEsDa6Z36GCghVzOHmvncTfk14eIWRfLdeaxsZ55iAbA7hT+670pI4V?=
 =?us-ascii?Q?wMSx+wr1WFG5xt4rQZJoS8wIoYVZRgKisH6SfgNANX9c9tNQs3/cImeUagvM?=
 =?us-ascii?Q?o2ttV0AT49LCToTqkSxz65/skPpNoK39Xvjve1aKBZnCHQ6HwDqdNYtgE2w2?=
 =?us-ascii?Q?YQSI1KMlT2JCP9slVLHP4FLUxTyjnIK3iCCyU/23BzXMgjNMM2a80Gm+oNvB?=
 =?us-ascii?Q?zFPcV8+QToNdZ/f1bc+gR0pg1G0JI9a/qioMtJQQ91WKMcLELgxZJEfkI9io?=
 =?us-ascii?Q?nhKZVZIdKYOstIojYb6ubr1Htf8l2cETuyFlNYZmP9tUGYUsu2JRMMlLL57S?=
 =?us-ascii?Q?RIaRPig+C+w6fsZvxoc4ESAUyhc2Gxb3bWeNC5arMoy0vql1Hdnt6wTVyv4U?=
 =?us-ascii?Q?RbtuZdRAjRR2wau4jgm/NZhYa06s/b86k68f4CwnbZSWmCWGeZ+VY2fxEagK?=
 =?us-ascii?Q?PNC+TAasJSUsz9KT3eKeEVr1JP8xq4Rzz+6SpaNmRat+4saKq8YmFUSFIWnH?=
 =?us-ascii?Q?3sCCNdf/a1S+/zMwwctdfVcJm6GWzZSBFcyF46BJyICnnbfGhXrvWorVpEVb?=
 =?us-ascii?Q?hksprYLnSDNuTboBmKjE3IBqKQ3uYzwCaLJFa71aiyO/vi5o0DpLDc37WThd?=
 =?us-ascii?Q?JJdz1esbJ2qqpiWVhHEzZ6+2nBhAIGR0XIjtThV9gcWurAXJH8EwLfnj1txr?=
 =?us-ascii?Q?Zl4aAfYxtEAOUikrc9TgOO3BsmsZUDbv+OqGVy6SIVlIq+3bxhrvL8ptP/IT?=
 =?us-ascii?Q?15ONsDu09Ri6X/m2N6t+kcuK?=
X-OriginatorOrg: wdc.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 6407e6d3-c664-40c1-90ef-08d9898f3330
X-MS-Exchange-CrossTenant-AuthSource: CO6PR04MB7812.namprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2021 12:37:18.2721
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: qUKZJi0hS7ZxsWulxy2Z2nqNqL1ULCjmLrsYGmuTpVB1zWFI/YspCF9SW7nwlIaGq78RfrC7x95FakZ31BVxAA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7777
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

We add DT bindings documentation for the ACLINT MSWI and SSWI
devices found on RISC-V SOCs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 .../riscv,aclint-swi.yaml                     | 97 +++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
new file mode 100644
index 000000000000..f034c18f46bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT Software Interrupt Devices
+
+maintainers:
+  - Anup Patel <anup.patel@wdc.com>
+
+description:
+  RISC-V SOCs include an implementation of the M-level software interrupt
+  (MSWI) device and the S-level software interrupt (SSWI) device defined
+  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
+
+  The ACLINT MSWI and SSWI devices are documented in the RISC-V ACLINT
+  specification located at
+  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+  The ACLINT MSWI and SSWI devices directly connect to the M-level and
+  S-level software interrupt lines of various HARTs (or CPUs) respectively
+  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
+  parent interrupt controller for the ACLINT MSWI and SSWI devices.
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+            - sifive,fu540-c000-aclint-mswi
+          - const: riscv,aclint-mswi
+
+      - items:
+          - enum:
+            - vendor,chip-aclint-sswi
+          - const: riscv,aclint-sswi
+
+    description:
+      For ACLINT MSWI devices, it should be "<vendor>,<chip>-aclint-mswi"
+      and "riscv,aclint-mswi".
+      For ACLINT SSWI devices, it should be "<vendor>,<chip>-aclint-sswi"
+      and "riscv,aclint-sswi".
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 0
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+  interrupt-controller: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+  - interrupt-controller
+  - "#interrupt-cells"
+
+examples:
+  - |
+    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
+
+    interrupt-controller@2000000 {
+      compatible = "sifive,fu540-c000-aclint-mswi", "riscv,aclint-mswi";
+      interrupts-extended = <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>,
+                            <&cpu4intc 3>;
+      reg = <0x2000000 0x4000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
+    };
+
+  - |
+    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
+
+    interrupt-controller@2f00000 {
+      compatible = "vendor,chip-aclint-sswi", "riscv,aclint-sswi";
+      interrupts-extended = <&cpu1intc 1>,
+                            <&cpu2intc 1>,
+                            <&cpu3intc 1>,
+                            <&cpu4intc 1>;
+      reg = <0x2f00000 0x4000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
+    };
+...
-- 
2.25.1