Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [PATCH v2 00/17] arm64: Self-hosted trace related errata
 workarounds
To:     Will Deacon <will@kernel.org>
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com,
        james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org,
        mike.leach@linaro.org, mathieu.poirier@linaro.org,
        lcherian@marvell.com, coresight@lists.linaro.org
References: <20210921134121.2423546-1-suzuki.poulose@arm.com>
 <20211008073229.GB32625@willie-the-truck>
From:   Suzuki K Poulose <suzuki.poulose@arm.com>
Message-ID: <b2527493-d4ca-2c42-eb22-7e8ddbe50279@arm.com>
Date:   Fri, 8 Oct 2021 10:25:03 +0100
User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0)
 Gecko/20100101 Thunderbird/78.14.0
MIME-Version: 1.0
In-Reply-To: <20211008073229.GB32625@willie-the-truck>
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Language: en-GB
Content-Transfer-Encoding: 7bit
Precedence: bulk

Hi Will

On 08/10/2021 08:32, Will Deacon wrote:
> Hi Suzuki,
> 
> On Tue, Sep 21, 2021 at 02:41:04PM +0100, Suzuki K Poulose wrote:
>> This series adds CPU erratum work arounds related to the self-hosted
>> tracing. The list of affected errata handled in this series are :
>>
>>   * TRBE may overwrite trace in FILL mode
>>     - Arm Neoverse-N2	#2139208
>>     - Cortex-A710	#211985
>>
>>   * A TSB instruction may not flush the trace completely when executed
>>     in trace prohibited region.
>>
>>     - Arm Neoverse-N2	#2067961
>>     - Cortex-A710	#2054223
>>
>>   * TRBE may write to out-of-range address
>>     - Arm Neoverse-N2	#2253138
>>     - Cortex-A710	#2224489
>>
>> The series applies on the self-hosted/trbe fixes posted here [0].
>> A tree containing both the series is available here [1]
> 
> Any chance you could put the arch/arm64/ bits at the start of the series,
> please? That way, I can queue them on their own branch which can be shared
> with the coresight tree.

I could move the bits around. I have a question though.

Will, Catalin, Mathieu,

The workaround for these errata, at least two of them are
in the TRBE driver patches. Are we happy with enabling the Kconfig
entry in the kernel, without the CoreSight patches to implement the work
around ?

Suzuki